LCMXO2-256ZE-3TG100C datasheet(14/106 Pages) LATTICE

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2-10

Architecture

MachXO2 Family Data Sheet

Table 2-5. sysMEM Block Configurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be

loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero

pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such

that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block

can also be utilized as a ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on specific design inputs.

Single, Dual, Pseudo-Dual Port and FIFO Modes

Figure 2-8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM

modes, the input data and addresses for the ports are registered at the input of the memory array. The output data

of the memory is optionally registered at the memory array output.

Memory Mode

Configurations

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

FIFO

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

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