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LCMXO2-256ZE-3TG100C 数据表(PDF) 75 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3TG100C 数据表(HTML) 75 Page - Lattice Semiconductor |
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75 / 106 page  3-36 DC and Switching Characteristics MachXO2 Family Data Sheet sysCONFIG Port Timing Specifications I 2C Port Timing Specifications1, 2 SPI Port Timing Specifications 1 Symbol Parameter Min. Max. Units All Configuration Modes tPRGM PROGRAMN low pulse accept 55 — ns tPRGMJ PROGRAMN low pulse rejection — 25 ns tINITL INITN low time — 55 us tDPPINIT PROGRAMN low to INITN low — 70 ns tDPPDONE PROGRAMN low to DONE low — 80 ns tIODISS PROGRAMN low to I/O disable — 120 ns Slave SPI fMAX CCLK clock frequency — 66 MHz tCCLKH CCLK clock pulse width high 7.5 — ns tCCLKL CCLK clock pulse width low 7.5 — ns tSTSU CCLK setup time 2 — ns tSTH CCLK hold time 0 — ns tSTCO CCLK falling edge to valid output — 10 ns tSTOZ CCLK falling edge to valid disable — 10 ns tSTOV CCLK falling edge to valid enable — 10 ns tSCS Chip select high time 25 — ns tSCSS Chip select setup time 3 — ns tSCSH Chip select hold time 3 — ns Master SPI fMAX MCLK clock frequency — 133 MHz tMCLKH MCLK clock pulse width high 3.75 — ns tMCLKL MCLK clock pulse width low 3.75 — ns tSTSU MCLK setup time 5 — ns tSTH MCLK hold time 1 — ns tCSSPI INITN high to chip select low 100 200 ns tMCLK INITN high to first MCLK edge 0.75 1 us Symbol Parameter Min. Max. Units fMAX Maximum SCL clock frequency — 400 KHz 1. MachXO2 supports the following modes: • Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode) • Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode) 2. Refer to the I 2C specification for timing requirements. Symbol Parameter Min. Max. Units fMAX Maximum SCK clock frequency — 45 MHz 1. Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications table in this data sheet. |
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