bq76PL536APAP datasheet(42/60 Pages) TI

42 / 60 page

bq76PL536A

SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012

www.ti.com

CB_TIME REGISTER (0x33)

CBT[7]

–

CBT[5]

CBT[4]

CBT[3]

CBT[2]

CBT[1]

CBT[0]

The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63

minutes. When set to 0, no balancing can occur – balancing is effectively disabled.

[7]

Controls minutes/seconds counting resolution.

0 = Seconds (default)

1 = Minutes

[5..0]

Sets the time duration as scaled by CBT.7

ADC_CONVERT REGISTER (0x34)

–

CONV

The CONVERT_CTRL register is used to start conversions.

[0] (CONV):

This bit starts a conversion, using the settings programmed into the ADC_CONTROL[]

0 = No conversion (default)

1 = Initiate conversion. This bit is automatically reset after conversion begins, and always

returns 0 on READ.

SHDW_CTRL REGISTER (0x3a)

SHDW[7]

SHDW[6]

SHDW[5]

SHDW[4]

SHDW[3]

SHDW[2]

SHDW[1]

SHDW[0]

The SHDW_CTRL register controls writing to Group3 protected registers. Default at RESET = 0x00.

The value 0x35 must be written to this register to allow writing to Group3 protected registers in the range

0x40–0x4f. The register always returns 0x00 on read. The register is reset to 0x00 after any successful write,

including a write to non-Group3 registers. A read operation does not reset this register.

Writing the value 0x27 results in all Group3 protected registers being refreshed from OTP programmed values.

The register is reset to 0x00 after the REFRESH is complete.

Submit Documentation Feedback

Product Folder Links :bq76PL536A

bq76PL536APAP 数据表(PDF) 42 Page - Texas Instruments

bq76PL536APAP 数据表(HTML) 42 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载