bq76PL536APAP datasheet(25/60 Pages) TI

25 / 60 page

bq76PL536A

www.ti.com

SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012

Auxiliary Power Output (AUX)

The

bq76PL536A

provides

approximately

1-mA

auxiliary

power

output

that

controlled

via

IO_CONTROL[AUX]. This output is taken directly from REG50. The current drawn from this pin must be included

in the REG50 current-limit budget by the designer.

Undervoltage Lockout and Power-On Reset

The device incorporates two comparators to detect low VBAT conditions. The first detects low voltage where some

device digital operations are still available. The second, (POR) detects a voltage below which device operation is

not ensured.

UVLO

When the UVLO threshold voltage is sensed for a period

≥ UVLODELAY, the device is no longer able to make

accurate analog measurements and conversions. The ADC, cell-balancing and fault-detection circuitry are

disabled. The digital circuitry, including host CPU and vertical communications between ICs, is fully functional.

DEVICE_STATUS[].

Power-On Reset (POR)

When the POR voltage threshold or lower is sensed for a period

≥ UVLODELAY, the device is no longer able to

function reliably. The device is disabled, including all fault-detection circuitry, host SPI communications, vertical

communications, etc.

After the voltage rises above the hysteresis limit longer than the delay time, the device exits the reset state, with

all registers set to default conditions. The FAULT_STATUS[POR] bit is set and latched until reset by the host.

The device no longer has a valid address (DEVICE_ADDRESS[AR] = 0, ADDRESS_CONTROL[] = 0). The

device should be reprogrammed with a valid address, and any registers re-written if non-default values are

desired.

Reset Command

The bq76PL536Acan also be reset by writing the reset code (0xa5) to the RESET register. All devices respond to

a broadcast RESET command regardless of their current assigned address. The result is identical to a POR with

the exception that the normal POR period is reduced to several hundred microseconds.

Thermal Shutdown (TSD)

The bq76PL536Acontains an integrated thermal shutdown circuit whose sensor is located near the REG50 LDO

and has a threshold of TSD. When triggered, the REG50 regulator reduces its output voltage to zero, and the

ADC is turned off to conserve power. The thermal shutdown circuit has a built-in hysteresis that delays recovery

until the die has cooled slightly. When the thermal shutdown is active, the DEVICE_STATUS[TSD] bit is set. The

IO_CONTROL[SLEEP] and ALERT[SLEEP] bits also become set to reduce power consumption.

WARNING

The secondary protector settings are DISABLED in the TSD state.

CAUTION

Temperature measurement and monitoring do not function due to loss of power if the

thermistors are powered from the REG50 or AUX pins and TSD occurs. Protection-

dependent schemes implemented by the designer which depend on the REG50

voltage also may not function as a result of loss of the REG50 output.

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