bq76PL536APAP datasheet(13/60 Pages) TI

13 / 60 page

t CS,LEAD

t CS,LAG

t(SCLK )

SCLK

t(HIGH)

t(LOW)

SDI

tSU,SDI

tHD,SDI

SDO

tACC

tVALID, SDO

tDIS

t CS _ DLY

bq76PL536A

www.ti.com

SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012

AC TIMING CHARACTERISTICS

SPI DATA INTERFACE

Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 85°C and VBAT = 7.2 V

to 27 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

fSCLK

SCLK frequency(1)

250

1000

kHz

SCLKDC

SCLK_H duty cycle, t(HIGH) / t(SCLK) or t(LOW) / t(SCLK)

40%

60%

tCS,LEAD

CS_H lead time, CS_H low to clock

SCLK/2

tCS,LAG

CS_H lag time. Last clock to CS_H high

SCLK/2

tCS,DLY

CS_H high to CS_H low (inter-packet delay requirement)

µs

tACC

CS_H access time(2): CS_H low to SDO_H data out

125

250

CS_H disable time(2): CS_H high to SDO_H high

tDIS

2.5

2.7

µs

impedance

tSU,SDI

SDI_H input-data setup time

tHD,SDI

SDI_H input-data hold time

SDO_H output-data valid time

tVALID,SDO

CL ≤ 20 pF

110

SCLK_H edge to SDO_H valid

(1)

Maximum SCLK frequency is limited by the number of bq76PL536A devices in the vertical stack. The maximum listed here may not be

realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing, etc.

See text for details.

(2)

Time listed is for single device.

Figure 3. SPI Host Interface Timing

Submit Documentation Feedback

Product Folder Links :bq76PL536A

bq76PL536APAP 数据表(PDF) 13 Page - Texas Instruments

bq76PL536APAP 数据表(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载