bq76PL536APAP datasheet(19/60 Pages) TI

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bq76PL536A

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SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012

Conversion Time Control

The ADC conversion time is fixed at approximately 6 µs per converted channel, plus 6 µs overhead at the start of

the conversion. Total conversion time (µs) is approximately 6 × num_channels + 6.

Automatic vs Manual Control

The ADC_CONTROL[ADC_ON] bit controls powering up the ADC section and the main bandgap reference. If

the bit is set to 1, the internal circuits are powered on, and current consumption by the part increases.

Conversions begin immediately on command. The host CPU should wait >500 µs before initiating the first

conversion after setting this bit.

If the ADC_ON bit is false, an additional 500 µs is required to stabilize the reference before conversions begin.

If the sampling interval (time between conversions) used is less than ~10 ms, manual mode should be selected

to avoid shifting the voltage reference, leading to inaccuracy in the measurements.

ADC Application Notes

Anti-Aliasing Filter

An anti-aliasing filter is required for each VCn input VC6–VC2, consisting of a 1-k

Ω, 1% series resistor and 100-

nF capacitor. The same filter is used, but with a 1-µF capacitor for the VC1 and VC0 sections. Good-quality

components should be used. A 1% resistor is recommended, because the resistor creates a small error by

forming a voltage divider with the input impedance of the part. The part is factory-trimmed to compensate for the

error introduced by the filter.

Secondary Protection

The bq76PL536A integrates dedicated overvoltage and undervoltage fault detection for each cell and two

overtemperature fault detection inputs for each device. The protection circuits use a separate band-gap reference

from the ADC system and operate independently. The protector also uses separate I/O pins from the main

communications bus, and therefore is capable of signaling faults in hardware without intervention from the host

CPU.

Protector Functionality

When a fault state is detected, the respective fault flag in the FAULT_STATUS[] or ALERT_STATUS[] registers

is set. All flags in the FAULT and ALERT registers are then ORed into the DEVICE_STATUS[] FAULT and

ALERT bits. The FAULT and ALERT bits in DEVICE_STATUS[] in turn cause the hardware FAULT_S or

ALERT_S pin to be set. The bits in DEVICE_STATUS[] and the hardware pins are latched until reset by the host

via SPI command, ensuring that the host CPU does not miss an event.

A separate timer is provided for each fault source (cell overvoltage, cell undervoltage, overtemperature) to

prevent false alarms. Each timer is programmable from 100 µs to more than 3 s. The timers may also be

disabled, which causes fault conditions to be sensed immediately and not latched.

The clearing of the FAULT or ALERT flag (and pin) occurs when the respective flag is written to a 1, which also

restarts the respective fault timer. This also clears the FAULT_S (_H) or ALERT_S (_H) pin. If the actual fault

remains present, the FAULT (ALERT) pin is again asserted at the expiration of the timer. This cycle repeats until

the cause of the fault is removed.

On exit from the SLEEP state, the COV, CUV, and OT fault comparators are disabled for approximately 200 µs

to allow internal circuitry to stabilize and prevent false error condition detection.

Using the Protector Functions With 3-5 Cells

The OV/UV condition can be ignored for unused channels by setting the FUNCTION_CONFIG[CNx] bits to the

maximum number of cells connected to the device. If fewer than 6 cells are configured, the corresponding OV/UV

faults are ignored. For example, if the FUNCTION_CONFIG[] bits are set to xxxx 1000, then the OV/UV

comparators are disabled for cells 5 and 6. Correct setting of this register prevents spurious false alarms.

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