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bq76PL536APAP 数据表(PDF) 23 Page - Texas Instruments

部件名 bq76PL536APAP
功能描述  3 to 6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for Applications
PDF  60 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

bq76PL536APAP 数据表(HTML) 23 Page - Texas Instruments

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bq76PL536A
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SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012
Table 2. Fault Detection Summary
SIGNALING
FAULT
DETECTION
PIN
DEVICE_STATUS
X_STATUS BIT SET
BIT SET
HSEL = 1
HSEL = 0
EPROM double bit
ECC logic fault detected
FAULT_S
FAULT_H
FAULT
FAULT_STATUS[I_FAULT]
error
FORCE
User set FORCE bit
FAULT_S
FAULT_H
FAULT
FAULT_STATUS[FORCE]
POR
Power-on reset occurred
FAULT_S
FAULT_H
FAULT
FAULT_STATUS[POR]
CRC(1)
CRC fail on received packet
FAULT_S
FAULT_H
FAULT
FAULT_STATUS[CRC]
CUV
VCx < VUV for tUV
FAULT_S
FAULT_H
FAULT
FAULT_STATUS[CUV]
COV
VCx > VOV for tOV
FAULT_S
FAULT_H
FAULT
FAULT_STATUS[COV]
AR
Address
≠ (0x01→ 0x3e)
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[AR]
Protected-register
Parity not even in protected
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[PARITY]
parity error
register
EPROM single-bit
ECC logic fault detected and
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[ECC_COR]
error
corrected
FORCE
User set FORCE bit
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[FORCE]
Die temperature
Thermal shutdown
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[TSD]
TSDTHRESHOLD
SLEEP
IC exited SLEEP mode
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[SLEEP]
OT2
VTS2 > VOT for tOT
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[OT2]
OT1
VTS1 > VOT for tOT
ALERT_S
ALERT_H
ALERT
ALERT_STATUS[OT1]
(1)
The CRC fault may be prevented from setting the FAULT pin by setting IO_CONFIG[7] = 1. The FAULT_STATUS[CRC] bit is still set
when CRC error is detected, but the FAULT pin remains de-asserted.
Fault Recovery Procedure
When any error flag in DEVICE_STATUS[], FAULT_STATUS[], or ALERT_STATUS[] is set and latched, the
state can only be cleared by host communication via SPI. Writing to the respective FAULT_STATUS or
ALERT_STATUS register bit with a 1 clears the latch for that bit. The exceptions are the two FORCE bits, which
are cleared by writing a 0 to the bit.
The FAULT_STATUS[] and ALERT_STATUS[] register bits are read-only, with the exception of the FORCE bit,
which may be directly written to either a 1 or 0.
Secondary Protector Built-In Self-Test Features
The secondary protector functions have built-in test for verifying the connections through the signal chain of ICs
in the stack back to the host CPU. This verifies the wiring, connections, and signal path through the ICs by
forcing a current through the signal path.
To implement this feature, host firmware should set the FAULT[FORCE] or ALERT[FORCE] bit in the top-most
device in the stack. The device asserts the associated pin on the South interface, and it propagates down the
stack, back to the base device. The base device in turn asserts the FAULT_H (ALERT_H) pin to the host,
allowing the host to check for the received signal and thereby verify correct operation.
CELL BALANCING
The bq76PL536A has six dedicated outputs (CB1…CB6) that can be used to control external N-FETs as part of
a cell balancing system. The implementation of appropriate algorithms is controlled by the system host. The
CB_CTRL[CBAL1–6] bits control the state of each of the outputs. The outputs are copied from the bit state of the
CB_CTRL register, i.e., a 1 in this register activates the external balance FET by placing a high on the
associated pin.
The CBx pins switch between approximately the positive and negative voltages of the cell across which the
external FET is connected. This allows the use of a small, low-cost N-FET in series with a power resistor to
provide cell balancing.
Copyright © 2011–2012, Texas Instruments Incorporated
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