AD9857SLASHPCB datasheet(16/40 Pages) AD

16 / 40 page

AD9857

Rev. C | Page 16 of 40

SINGLE-TONE MODE

A block diagram of the AD9857 operating in the single-tone

mode is shown in Figure 19. In the single-tone mode, both the

I and Q data paths are disabled from the 14-bit parallel data

port up to and including the modulator. The PDCLK/ FUD pin

is an input and functions as a frequency update (FUD) control

signal. This is necessary because the frequency tuning word is

programmed via the asynchronous serial port. The FUD signal

causes the new frequency tuning word to become active.

In single-tone mode, the cosine portion of the DDS serves as

the signal source. The output signal consists of a single

frequency as determined by the tuning word stored in the

appropriate control register, per each profile.

In the single-tone mode, no 14-bit parallel data is applied to the

AD9857. The internal DDS core is used to produce a single

frequency signal according to the tuning word. The single-tone

signal then moves toward the output, where the inverse SINC

filter and the output scaling can be applied. Finally, the digital

single-tone signal is converted to the analog domain by the

14-bit DAC.

14-BIT

DAC

DAC_RSET

IOUT

OUTPUT

SCALE

VALUE

REFCLK

MODE

CONTROL

PLL

LOCK

CLOCK

INPUT

MODE

AD9857

PDCLK/

FUD

INVERSE

SINC

FILTER

TUNING

WORD

TIMING AND CONTROL

DDS

CORE

CLOCK

MULTIPLIER

(4 – 20 )

PROFILE

SELECT

LOGIC

CONTROL REGISTERS

RESET

SERIAL

PORT

PS0

PS1

POWER-

DOWN

LOGIC

DIGITAL

POWER-

DOWN

Figure 19. Single-Tone Mode

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