AD9857SLASHPCB datasheet(18/40 Pages) AD

18 / 40 page

AD9857

Rev. C | Page 18 of 40

SIGNAL PROCESSING PATH

To better understand the operation of the AD9857 it is helpful

to follow the signal path from input, through the device, to the

output, examining the function of each block (refer to Figure 1).

The input to the AD9857 is a 14-bit parallel data path. This

assumes that the user is supplying the data as interleaved I and

Q values. Any encoding, interpolation, and pulse shaping of the

data stream should occur before the data is presented to the

AD9857 for upsampling.

The AD9857 demultiplexes the interleaved I and Q data into

two separate data paths inside the part. This means that the

input sample rate (fDATA), the rate at which 14-bit words are

presented to the AD9857, must be 2× the internal I/Q Sample

Rate (fIQ), the rate at which the I/Q pairs are processed. In other

words, fDATA = 2 × fIQ.

From the input demultiplexer to the quadrature modulator, the

data path of the AD9857 is a dual I/Q path.

All timing within the AD9857 is provided by the internal

system clock (SYSCLK) signal. The externally provided

reference clock signal may be used as is (1×), or multiplied by

the internal clock multiplier (4×−20×) to generate the SYSCLK.

All other internal clocks and timing are derived from the

SYSCLK.

INPUT DATA ASSEMBLER

In the quadrature modulation or interpolating DAC modes, the

device accepts 14-bit, twos complement data at its parallel data

port. The timing of the data supplied to the parallel port may be

easily facilitated with the PDCLK/FUD pin of the AD9857,

which is an output in the quadrature modulation mode and the

interpolating DAC mode. In the single-tone mode, the same pin

becomes an input to the device and serves as a frequency

update (FUD) strobe.

Frequency control words are programmed into the AD9857 via

the serial port (see the Control Register description). Because

the serial port is an asynchronous interface, when programming

new frequency tuning words into the on-chip profile registers,

the AD9857’s internal frequency synthesizer must be

synchronized with external events. The purpose of the FUD

input pin is to synchronize the start of the frequency

synthesizer to the external timing requirements of the user. The

rising edge of the FUD signal causes the frequency tuning word

of the selected profile (see the Profile section) to be transferred

to the accumulator of the DDS, thus starting the frequency

synthesis process.

After loading the frequency tuning word to a profile, a FUD

signal is not needed when switching between profiles using the

two profile select pins (PS0, PS1). When switching between

profiles, the frequency tuning word in the profile register

becomes effective.

In the quadrature modulation mode, the PDCLK rate is twice

the rate of the I (or Q) data rate. The AD9857 expects

interleaved I and Q data words at the parallel port with one

word per PDCLK rising edge. One I word and one Q word

together comprise one internal sample. Each sample is

propagated along the internal data pathway in parallel.

In the interpolating DAC mode, however, the PDCLK rate is the

same as the I data rate because the Q data path is inactive. In

this mode, each PDCLK rising edge latches a data word into the

I data path.

The PDCLK is provided as a continuous clock (i.e., always

active). However, the assertion of PDCLK may be optionally

qualified internally by the PLL lock indicator if the user elects

to set the PLL lock control bit in the appropriate control register.

Data supplied by the user to the 14-bit parallel port is latched

into the device coincident with the rising edge of the PDCLK.

In the quadrature modulation mode, the rising edge of the

TxENABLE signal is used to synchronize the device. While

TxENABLE is in the Logic 0 state, the device ignores the 14-bit

data applied to the parallel port and allows the internal data

path to be flushed by forcing 0s down the I and Q data pathway.

On the rising edge of TxENABLE, the device is ready for the

first I word. The first I word is latched into the device

coincident with the rising edge of PDCLK. The next rising edge

of PDCLK latches in a Q word, etc., until TxENABLE is set to a

Logic 0 state by the user.

When in the quadrature modulation mode, it is important that

the user ensure that an even number of PDCLK intervals are

observed during any given TxENABLE period. This is because

the device must capture both an I and a Q value before the data

can be processed along the internal data pathway.

The timing relationship between TxENABLE, PDCLK, and

DATA is shown in Figure 21 and Figure 22.

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