AD9857SLASHPCB datasheet(22/40 Pages) AD

22 / 40 page

AD9857

Rev. C | Page 22 of 40

)

The equation relating output frequency (fOUT) of the AD9857

digital modulator to the frequency tuning word (FTWORD)

and the system clock (SYSCLK) is

(

SYSCLK

FTWORD

OUT

(2)

where fOUT and SYSCLK frequencies are in Hz and FTWORD is

a decimal number from 0 to 2,147,483,647 (231−1).

For example, find the FTWORD for fOUT = 41 MHz and

SYSCLK = 122.88 MHz

If fOUT = 41 MHz and SYSCLK = 122.88 MHz, then

hex

FTWORD

AAAAB

556

(3)

Loading 556AAAABh into Control Bus Registers 08h–0Bh

(for Profile 1) programs the AD9857 for fOUT = 41 MHz, given a

SYSCLK frequency of 122.88 MHz.

INVERSE SINC FILTER

The sampled carrier data stream is the input to the digital-to-

analog converter (DAC) integrated onto the AD9857. The

DAC output spectrum is shaped by the characteristic sin(x)/x

(or SINC) envelope, due to the intrinsic zero-order hold effect

associated with DAC-generated signals. Because the shape of

the SINC envelope is well known, it can be compensated for.

This envelope restoration function is provided by the optional

inverse SINC filter preceding the DAC. This function is

implemented as an FIR filter, which has a transfer function that

is the exact inverse of the SINC response. When the inverse

SINC filter is selected, it modifies the incoming data stream so

that the desired carrier envelope, which would otherwise be

shaped by the SINC envelope, is restored. However, this

correction is only complete for carrier frequencies up to

approximately 45% of SYSCLK.

Note also that the inverse SINC filter introduces about a 3.5 dB

loss at low frequencies as compared to the gain with the inverse

SINC filter turned off. This is done to flatten the overall gain

from dc to 45% of SYSCLK.

The inverse SINC filter can be bypassed if it is not needed. If the

inverse SINC filter is bypassed, its clock is stopped, thus

reducing the power dissipation of the part.

OUTPUT SCALE MULTIPLIER

An 8-bit multiplier (output scale value in the block diagram)

preceding the DAC provides the user with a means of adjusting

the final output level. The multiplier value is programmed via

the appropriate control registers, per each profile. The LSB

weight is 2–7, which yields a multiplier range of 0 to 1.9921875,

or nearly 2×. Because the quadrature modulator has an intrinsic

loss of 3 dB (1/√2), programming the multiplier for a value of

√2) restores the data to the full-scale range of the DAC when

the device is operating in the quadrature modulation mode.

Because the AD9857 defaults to the Modulation mode, the

default value for the multiplier is B5h (which corresponds

to √2).

Programming the output scale multiplier to unity gain (80h)

bypasses the stage, reducing power dissipation.

14-BIT D/A CONVERTER

A 14-bit digital-to-analog converter (DAC) is used to convert

the digitally processed waveform into an analog signal. The

worst-case spurious signals due to the DAC are the harmonics

of the fundamental signal and their aliases (please see the

Analog Devices DDS Technical Tutorial, accessible from the

DDS Technical Library at www.analog.com/dds for a detailed

explanation of aliases). The wideband 14-bit DAC in the

AD9857 maintains spurious-free dynamic range (SFDR)

performance of −60 dBc up to AOUT = 42 MHz and −55 dBc up

to AOUT = 65 MHz.

The conversion process produces aliased components of the

fundamental signal at n × SYSCLK ± FCARRIER (n = 1, 2, 3).

These are typically filtered with an external RLC filter at the

DAC output. It is important for this analog filter to have a

sufficiently flat gain and linear phase response across the

bandwidth of interest to avoid modulation impairments.

The AD9857 provides true and complemented current outputs

on AOUT and AOUT, respectively. The full-scale output current is

set by the RSET resistor at DAC_RSET. The value of RSET for a

particular IOUT is determined using the following equation:

IOUT

RSET

(4)

For example, if a full-scale output current of 20 mA is desired,

then RSET = (39.93/0.02), or approximately 2 kΩ. Every

doubling of the RSET value halves the output current.

The full-scale output current range of the AD9857 is 5 mA−20

mA. Full-scale output currents outside of this range degrade

SFDR performance. SFDR is also slightly affected by output

matching; the two outputs should be terminated equally for best

SFDR performance.

The output load should be located as close as possible to the

AD9857 package to minimize stray capacitance and inductance.

The load may be a simple resistor to ground, an op amp

current-to- voltage converter, or a transformer-coupled circuit.

Driving an LC filter without a transformer requires that the

filter be doubly terminated for best performance. Therefore, the

filter input and output should both be resistively terminated

with the appropriate values. The parallel combination of the

two terminations determines the load that the AD9857 sees

for signals within the filter pass band. For example, a

50 Ω terminated input/ output low-pass filter looks like a

25 Ω load to the AD9857.

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