AD9857SLASHPCB datasheet(17/40 Pages) AD

17 / 40 page

AD9857

Rev. C| Page 17 of 40

INTERPOLATING DAC MODE

A block diagram of the AD9857 operating in the interpolating

DAC mode is shown in Figure 20. In this mode, the DDS and

modulator are both disabled and only the I data path is active.

The Q data path is disabled from the 14-bit parallel data port up

to and including the modulator.

As in the quadrature modulation mode, the PDCLK pin is an

output and functions as a clock which serves to synchronize the

input of data to the AD9857. Unlike the quadrature modulation

mode, however, the PDCLK operates at the rate of the I data

path. This is because only I data is being presented to the

parallel port as opposed to the interleaved I/Q format of the

quadrature modulation mode.

In the Interpolating DAC mode, the baseband data supplied at

the parallel port remains at baseband at the output; that is, no

modulation takes place. However, a sample rate conversion

takes place based on the programmed interpolation rate. The

interpolation hardware performs the necessary signal

processing required to eliminate the aliased images at baseband

that would otherwise result from a sample rate conversion. The

interpolating DAC function is effectively an oversampling

operation with the original input spectrum intact but sampled

at a higher rate.

14-BIT

DAC

DAC_RSET

IOUT

OUTPUT

SCALE

VALUE

REFCLK

MODE

CONTROL

PLL

LOCK

CLOCK

INPUT

MODE

AD9857

PARALLEL

DATA IN

(14-BIT)

PDCLK/

FUD

INVERSE

CIC FILTER

INV

CIC

(4 )

CIC

(2 - 63 )

FIXED

INTER-

POLATOR

PROGRAMMABLE

INTERPOLATOR

INVERSE

SINC

FILTER

TIMING AND CONTROL

CLOCK

MULTIPLIER

(4 – 20 )

PROFILE

SELECT

LOGIC

CONTROL REGISTERS

RESET

CIC

OVERFLOW

SERIAL

PORT

PS0

PS1

POWER-

DOWN

LOGIC

DIGITAL

POWER-

DOWN

TxENABLE

Figure 20. Interpolating DAC Mode

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