AD9857SLASHPCB datasheet(24/40 Pages) AD

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AD9857

Rev. C | Page 24 of 40

INPUT DATA PROGRAMMING

CONTROL INTERFACE—SERIAL I/O

The AD9857 serial port is a flexible, synchronous, serial

communications port allowing easy interface to many industry-

standard microcontrollers and microprocessors. The serial I/O

is compatible with most synchronous transfer formats,

including both the Motorola 6905/11 SPI and Intel 8051 SSR

protocols.

The interface allows read/write access to all registers that

configure the AD9857. Single or multiple byte transfers are

supported as well as MSB first or LSB first transfer formats. The

AD9857’s serial interface port can be configured as a single pin

I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the

AD9857. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9857, coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9857 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication

cycle. The Phase 1 instruction byte defines whether the

upcoming data transfer is read or write, the number of bytes in

the data transfer (1-4), and the starting register address for the

first byte of the data transfer.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9857. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9857

and the system controller. Phase 2 of the communication cycle

is a transfer of 1, 2, 3, or 4 data bytes as determined by the

instruction byte. Typically, using one communication cycle in a

multibyte transfer is the preferred method. However, single-byte

communication cycles are useful to reduce CPU overhead when

be to write the AD9857 SLEEP bit.

At the completion of any communication cycle, the AD9857

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle.

All data input to the AD9857 is registered on the rising edge of

SCLK. All data is driven out of the AD9857 on the falling edge

of SCLK.

Figure 27 and Figure 28 illustrate the data write and data read

operations on the AD9857 serial port. Figure 29 through

Figure 32 show the general operation of the AD9857 serial port.

tPRE

tSCLK

tSCLKPWH

tSCLKPWL

tDSU

tDHLD

SCLK

SDIO

1ST BIT

2ND BIT

SYMBOL

DEFINITION

MIN

tPRE

tSCLK

tDSU

tSCLKPWH

tSCLKPWL

tDHLD

CS SETUP TIME

PERIOD OF SERIAL DATA CLOCK

SERIAL DATA SETUP TIME

SERIAL DATA CLOCK PULSE WIDTH HIGH

SERIAL DATA CLOCK PULSE WIDTH LOW

SERIAL DATA HOLD TIME

40ns

100ns

30ns

40ns

0ns

Figure 27. Timing Diagram for Data Write to AD9857

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