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OMAP3530ECUS 数据表(PDF) 189 Page - Texas Instruments |
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OMAP3530ECUS 数据表(HTML) 189 Page - Texas Instruments |
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189 / 264 page  OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode (continued) TIMING CONDITION PARAMETER VALUE UNIT CLOAD Output load capacitance 8.6 pF Table 6-29. ISP Timing Requirements – 12-Bit SYNC Normal – Interlaced Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX ISP17 tc(pclk) Cycle time(2), cam_pclk period 13.3 22.2 ns ISP18 tW(pclkH) Typical pulse duration, cam_pclk high 0.5*P(3) 0.5*P(3) ns ISP18 tW(pclkL) Typical pulse duration, cam_pclk low 0.5*P(3) 0.5*P(3) ns tdc(pclk) Duty cycle error, cam_pclk 667 1111 ps tj(pclk) Cycle jitter(4), cam_pclk 133 200 ps ISP19 tsu(dV-pclkH) Setup time, cam_d[11:0] valid before cam_pclk 1.82 3.25 ns rising edge ISP20 th(pclkH-dV) Hold time, cam_d[11:0] valid after cam_pclk rising 1.82 3.25 ns edge ISP21 tsu(dV-vsH) Setup time, cam_vs valid before cam_pclk rising 1.82 3.25 ns edge ISP22 th(pclkH-vsV) Hold time, cam_vs valid after cam_pclk rising edge 1.82 3.25 ns ISP23 tsu(dV-hsH) Setup time, cam_hs valid before cam_pclk rising 1.82 3.25 ns edge ISP24 th(pclkH-hsV) Hold time, cam_hs valid after cam_pclk rising edge 1.82 3.25 ns ISP25 tsu(dV-hsH) Setup time, cam_wen valid before cam_pclk rising 1.82 3.25 ns edge ISP26 th(pclkH-hsV) Hold time, cam_wen valid after cam_pclk rising 1.82 3.25 ns edge ISP27 tsu(dV-fldH) Setup time, cam_fld valid before cam_pclk rising 1.82 3.25 ns edge ISP28 th(pclkH-fldV) Hold time, cam_fld valid after cam_pclk rising edge 1.82 3.25 ns (1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) Related with the input maximum frequency supported by the ISP module. (3) P = cam_lclk period in ns. (4) Maximum cycle jitter supported by cam_pclk input clock. Table 6-30. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX ISP15 tc(xclk) Cycle time(1), cam_xclk period 4.6 4.6 ns ISP16 tW(xclkH) Typical pulse duration, cam_xclk high 0.5*PO(2) 0.5*PO(2) ns ISP16 tW(xclkL) Typical pulse duration, cam_xclk low 0.5*PO(2) 0.5*PO(2) ns tdc(xclk) Duty cycle error, cam_xclk 231 231 ps tj(xclk) Jitter standard deviation(3), cam_xclk 33 33 ps tR(xclk) Rise time, cam_xclk 0.93 0.93 ns tF(xclk) Fall time, cam_xclk 0.93 0.93 ns (1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module. Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 (2) PO = cam_xclk period in ns. (3) The jitter probability density can be approximated by a Gaussian function. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 189 |
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