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OMAP3530ECUS 数据表(PDF) 56 Page - Texas Instruments

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部件名 OMAP3530ECUS
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECUS 数据表(HTML) 56 Page - Texas Instruments

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
U17
NA
mcbsp1_dx
0
IO
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
mcspi4_simo
1
IO
mcbsp3_dx
2
IO
gpio_158
4
IO
safe_mode
7
-
V17
NA
mcbsp1_fsr
0
IO
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
cam_global_r
2
IO
eset
gpio_157
4
IO
safe_mode
7
-
P20
NA
mcbsp1_fsx
0
IO
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
mcspi4_cs0
1
IO
mcbsp3_fsx
2
IO
gpio_161
4
IO
safe_mode
7
-
R18
NA
mcbsp2_clkx
0
IO
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_117
4
IO
safe_mode
7
-
T18
NA
mcbsp2_dr
0
I
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_118
4
IO
safe_mode
7
-
R19
NA
mcbsp2_dx
0
IO
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_119
4
IO
safe_mode
7
-
U18
NA
mcbsp2_fsx
0
IO
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_116
4
IO
safe_mode
7
-
P9
NA
mcspi1_clk
0
IO
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
mmc2_dat4
1
IO
gpio_171
4
IO
safe_mode
7
-
R7
NA
mcspi1_cs0
0
IO
H
H
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
mmc2_dat7
1
IO
gpio_174
4
IO
safe_mode
7
-
R9
NA
mcspi1_cs2
0
O
H
H
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
mmc3_clk
3
O
gpio_176
4
IO
safe_mode
7
-
P8
NA
mcspi1_simo
0
IO
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
mmc2_dat5
1
IO
gpio_172
4
IO
safe_mode
7
-
P7
NA
mcspi1_somi
0
IO
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
mmc2_dat6
1
IO
(5)
The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
TERMINAL DESCRIPTION
56
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