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OMAP3530ECUS 数据表(PDF) 30 Page - Texas Instruments |
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OMAP3530ECUS 数据表(HTML) 30 Page - Texas Instruments |
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30 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BALL TOP PIN NAME MODE [4] TYPE [5] BALL BALL RESET REL. POWER [9] HYS [10] BUFFER PULLUP IO CELL [13] BOTTOM [1] [2] [3] RESET RESET REL. MODE [8] STRENG TH /DOWN STATE [6] STATE [7] (mA) [11] TYPE [12] safe_mode 7 K1 M2 gpmc_d0 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS L1 M1 gpmc_d1 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS L2 N2 gpmc_d2 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS P2 N1 gpmc_d3 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS T1 R2 gpmc_d4 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS V1 R1 gpmc_d5 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS V2 T2 gpmc_d6 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS W2 T1 gpmc_d7 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS H2 AB3 gpmc_d8 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 K2 AC3 gpmc_d9 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 P1 AB4 gpmc_d10 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 R1 AC4 gpmc_d11 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 R2 AB6 gpmc_d12 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 T2 AC6 gpmc_d13 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 W1 AB7 gpmc_d14 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 Y1 AC7 gpmc_d15 0 IO H H 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_51 4 IO safe_mode 7 G4 Y2 gpmc_ncs0 0 O 1 1 0 vdds_ mem No 4 NA LVCMOS H3 Y1 gpmc_ncs1 0 O H 1 0 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_52 4 IO safe_mode 7 V8 NA gpmc_ncs2 0 O H H 7 vdds_ mem Yes 4 PU/ PD LVCMOS gpio_53 4 IO safe_mode 7 U8 NA gpmc_ncs3 0 O H H 7 vdds_ mem Yes 4 PU/ PD LVCMOS sys_ 1 I ndmareq0 gpio_54 4 IO safe_mode 7 T8 NA gpmc_ncs4 0 O H H 7 vdds_ mem Yes 4 PU/ PD LVCMOS sys_ 1 I ndmareq1 mcbsp4_ 2 IO clkx gpt9_pwm_e 3 IO vt gpio_55 4 IO safe_mode 7 R8 NA gpmc_ncs5 0 O H H 7 vdds_ mem Yes 4 PU/ PD LVCMOS TERMINAL DESCRIPTION 30 Submit Documentation Feedback |
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