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OMAP3530ECUS 数据表(PDF) 60 Page - Texas Instruments

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部件名 OMAP3530ECUS
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECUS 数据表(HTML) 60 Page - Texas Instruments

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
AE14
NA
sys_clkout1
0
O
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_10
4
IO
safe_mode
7
-
W11
NA
sys_clkout2
0
O
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_186
4
IO
safe_mode
7
-
W15
NA
sys_clkreq
0
IO
0
1
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_1
4
IO
safe_mode
7
-
V16
NA
sys_nirq
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_0
4
IO
safe_mode
7
-
V13
NA
sys_nrespwr
0
I
Z
I
NA
vdds
Yes
NA
NA
LVCMOS
on
AD7
AA5
sys_nreswar
0
IOD
0
1 (PU)
0
vdds
Yes
4
PU100/
LVCMOS
m
PD100
gpio_30
4
IO
Open Drain
safe_mode
7
-
V12
NA
sys_off_mod
0
O
0
L
7
vdds
Yes
4
PU100/
LVCMOS
e
PD100
gpio_9
4
IO
safe_mode
7
-
AF19
NA
sys_xtalin
0
I
Z
I
NA
vdds
Yes
NA
NA
LVCMOS
AF20
NA
sys_xtalout
0
O
Z
O
NA
vdds
Yes
NA
NA
LVCMOS
W26
NA
tv_out1
0
AO
Z
0
0
vdda_dac
No
8
NA
10-bit DAC
V26
NA
tv_out2
0
AO
Z
0
0
vdda_dac
No
8
NA
10-bit DAC
W25
NA
tv_vfb1
0
O
Z
NA
0
vdda_dac
No
2
NA
10-bit DAC
U24
NA
tv_vfb2
0
O
Z
NA
0
vdda_dac
No
2
NA
10-bit DAC
V23
NA
tv_vref
0
I
Z
NA
0
vdda_dac
No
NA
NA
10-bit DAC
AE20
NA
sys_32k
0
I
Z
I
NA
vdds
Yes
NA
NA
LVCMOS
A24
NA
cam_d2
0
I
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_101
4
IO
hw_dbg4
5
O
safe_mode
7
-
B24
NA
cam_d3
0
I
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_102
4
IO
hw_dbg5
5
O
safe_mode
7
-
D24
NA
cam_d4
0
I
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_103
4
IO
hw_dbg6
5
O
safe_mode
7
-
C24
NA
cam_d5
0
I
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_104
4
IO
hw_dbg7
5
O
safe_mode
7
-
D25
NA
cam_d10
0
I
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_109
4
IO
hw_dbg8
5
O
safe_mode
7
-
TERMINAL DESCRIPTION
60
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