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OMAP3530ECUS 数据表(PDF) 70 Page - Texas Instruments |
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OMAP3530ECUS 数据表(HTML) 70 Page - Texas Instruments |
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70 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 2-3. Ball Characteristics (CUS Pkg.) BALL BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] STATE [6] REL. STATE MODE [8] STRENG TH /DOWN TYPE [7] (mA) [11] [12] D7 sdrc_d0 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C5 sdrc_d1 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C6 sdrc_d2 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B5 sdrc_d3 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS D9 sdrc_d4 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS D10 sdrc_d5 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C7 sdrc_d6 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B7 sdrc_d7 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B11 sdrc_d8 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C12 sdrc_d9 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B12 sdrc_d10 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS D13 sdrc_d11 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C13 sdrc_d12 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B14 sdrc_d13 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS A14 sdrc_d14 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B15 sdrc_d15 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C9 sdrc_d16 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS E12 sdrc_d17 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B8 sdrc_d18 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B9 sdrc_d19 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C10 sdrc_d20 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B10 sdrc_d21 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS D12 sdrc_d22 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS E13 sdrc_d23 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS E15 sdrc_d24 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS D15 sdrc_d25 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C15 sdrc_d26 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B16 sdrc_d27 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C16 sdrc_d28 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS D16 sdrc_d29 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B17 sdrc_d30 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS B18 sdrc_d31 0 IO L Z 0 vdds_ mem Yes 4 PU/ PD LVCMOS C18 sdrc_ba0 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS D18 sdrc_ba1 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS A4 sdrc_a0 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS B4 sdrc_a1 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS D6 sdrc_a2 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS B3 sdrc_a3 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS B2 sdrc_a4 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS C3 sdrc_a5 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS E3 sdrc_a6 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS F6 sdrc_a7 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS E10 sdrc_a8 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS E9 sdrc_a9 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS E7 sdrc_a10 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS G6 sdrc_a11 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS G7 sdrc_a12 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS F7 sdrc_a13 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS F9 sdrc_a14 0 O 0 0 0 vdds_ mem No 4 NA LVCMOS A19 sdrc_ncs0 0 O 1 1 0 vdds_ mem No 4 NA LVCMOS B19 sdrc_ncs1 0 O 1 1 0 vdds_ mem No 4 NA LVCMOS A10 sdrc_clk 0 IO L 0 0 vdds_ mem Yes 4 PU/ PD LVCMOS A11 sdrc_nclk 0 O 1 1 0 vdds_ mem No 4 NA LVCMOS TERMINAL DESCRIPTION 70 Submit Documentation Feedback |
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