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OMAP3530ECUS 数据表(PDF) 72 Page - Texas Instruments

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部件名 OMAP3530ECUS
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECUS 数据表(HTML) 72 Page - Texas Instruments

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
www.ti.com
Table 2-3. Ball Characteristics (CUS Pkg.) (continued)
BALL
BALL TOP [2] PIN NAME [3] MODE [4]
TYPE [5]
BALL RESET BALL RESET RESET REL.
POWER [9]
HYS [10]
BUFFER
PULLUP
BOTTOM [1]
STATE [6]
REL. STATE
MODE [8]
STRENG TH
/DOWN TYPE
[7]
(mA) [11]
[12]
P2
gpmc_d6
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
R1
gpmc_d7
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
R2
gpmc_d8
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_44
4
IO
safe_mode
7
T2
gpmc_d9
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_45
4
IO
safe_mode
7
U1
gpmc_d10
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_46
4
IO
safe_mode
7
R3
gpmc_d11
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_47
4
IO
safe_mode
7
T3
gpmc_d12
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_48
4
IO
safe_mode
7
U2
gpmc_d13
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_49
4
IO
safe_mode
7
V1
gpmc_d14
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_50
4
IO
safe_mode
7
V2
gpmc_d15
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_51
4
IO
safe_mode
7
E2
gpmc_ncs0
0
O
1
1
0
vdds_ mem
No
4
NA
LVCMOS
D2
gpmc_ncs3
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq0
gpio_54
4
IO
safe_mode
7
F4
gpmc_ncs4
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq1
mcbsp4_ clkx 2
IO
gpt9_pwm_evt 3
IO
gpio_55
4
IO
safe_mode
7
G5
gpmc_ncs5
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq2
mcbsp4_dr
2
I
gpt10_pwm_e 3
IO
vt
gpio_56
4
IO
safe_mode
7
F3
gpmc_ncs6
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq3
mcbsp4_dx
2
IO
gpt11_pwm_e 3
IO
vt
gpio_57
4
IO
safe_mode
7
G4
gpmc_ncs7
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpmc_io_dir
1
O
TERMINAL DESCRIPTION
72
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