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OMAP3530ECUS 数据表(PDF) 206 Page - Texas Instruments |
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OMAP3530ECUS 数据表(HTML) 206 Page - Texas Instruments |
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206 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 6-56. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode (continued) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbspx_fsx valid after 0.5 0.5 ns mcbsp1_clkr /mcbspx_clkx active edge Table 6-57. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delay time, mcbsp1_clkr / mcbspx_clkx active edge to 0.7 14.8 0.7 29.6 ns mcbsp1_fsr / mcbspx_fsx valid (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). Table 6-58. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before Master 2.7 7.7 ns mcbspx_clkx active edge Slave 3.7 7.9 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after Master 1 1 ns mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time mcbspx_fsx valid before mcbspx_clkx active 3.7 7.9 ns edge B6 th(CLKXAE-FSXV) Hold time mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60 Table 6-59. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 16.6 0.7 33.1 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60 Table 6-60. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Receive Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before Master 5.6 12 ns mcbspx_clkx active edge Slave 5.8 12.2 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after mcbspx_clkx Master 1 1 ns active edge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active 5.8 12.2 ns edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 206 Submit Documentation Feedback |
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