OMAP3530ECUS datasheet(139/264 Pages) TI1

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4.2 Output Clock Specifications

sys_clkout

CO0

CO1

030-014

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:

• sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be

controlled by software or externally using sys_clkreq control. When the device is in the off state, the

sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the

device. The off state polarity of sys_clkout1 is programmable.

• sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output,

332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off

state polarity is programmable. This output is active only when the core domain is active.

Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics.

Table 4-10. sys_clkout1 Output Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency

12, 13, 16.8, 19.2, 26, or 38.4

MHz

Load capacitance(1)

f(max) = 38.4 MHz

f(max) = 26 MHz

(1)

The load capacitance is adapted to a frequency.

Table 4-11 details the sys_clkout1 output clock timing characteristics.

Table 4-11. sys_clkout1 Output Clock Switching Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

1 / CO0

Frequency

12, 13, 16.8, 19.2, 26, or 38.4

MHz

CO1

tw(CLKOUT1)

Pulse duration, sys_clkout1 low or high

0.40 *

0.60 *

tc(CLKOUT1)

CO2

tR(CLKOUT1)

Rise time, sys_clkout1(1)

5.5

CO3

tF(CLKOUT1)

Fall time, sys_clkout1(1)

5.5

(1)

With a load capacitance of 50 pF.

Figure 4-7. sys_clkout1 System Output Clock

Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics.

Table 4-12. sys_clkout2 Output Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency, sys_clkout2

322

MHz

Load capacitance(1)

f(max) = 166 MHz

(1)

The load capacitance is adapted to a frequency.

Table 4-13 details the sys_clkout2 output clock timing characteristics.

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CLOCK SPECIFICATIONS

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