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STM8AF6166 数据表(PDF) 31 Page - STMicroelectronics |
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STM8AF6166 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 89 page  STM8AF61xx, STM8AF62xx Memory and register map Doc ID 14952 Rev 6 31/89 0x00 501E Port G PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX(1) 0x00 5020 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 1. Depends on the external circuitry. Table 13. General hardware register map Address Block Register label Register name Reset status 0x00 505A Flash FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF 0x00 505D FLASH_FPR Flash protection register 0x00 0x00 505E FLASH_NFPR Flash complementary protection register 0xFF 0x00 505F FLASH_IAPSR Flash in-application programming status register 0x40 0x00 5060 to 0x00 5061 Reserved area (2 bytes) 0x00 5062 Flash FLASH_PUKR Flash Program memory unprotection register 0x00 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash FLASH_DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area (59 bytes) 0x00 50A0 ITC EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area (17 bytes) 0x00 50B3 RST RST_SR Reset status register 0xXX(1) 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK CLK_ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) Table 12. I/O port hardware register map (continued) Address Block Register label Register name Reset status |
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