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STM8AF6166 数据表(PDF) 50 Page - STMicroelectronics |
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STM8AF6166 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 89 page ![]() Electrical characteristics STM8AF61xx, STM8AF62xx 50/89 Doc ID 14952 Rev 6 Figure 8. fCPUmax versus VDD 1. This figure is valid only for STM8AF62xx devices. Table 24. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2(1) 1. Guaranteed by design, not tested in production - ∞ µs/V VDD fall time rate - 2(1) - ∞ tTEMP Reset release delay VDD rising - 3 - ms Reset generation delay VDD falling - 3 - µs VIT+ Power-on reset threshold(2) 2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is kept. The EEPROM programming sequence must not be initiated. - 2.65 2.8 2.95 V VIT- Brown-out reset threshold - 2.58 2.73 2.88 VHYS(BOR) Brown-out reset hysteresis -- 70(1) -mV fCPU [MHz] Supply voltage [V] 24 12 8 4 0 3.0 4.0 5.0 Functionality Functionality guaranteed @ TA -40 to 150 °C not guaranteed in this area 16 5.5 |
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