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AD6620

–30–

REV. A

PROGRAMMING THE AD6620

Initializing the AD6620

Before the AD6620 can be used to down convert and filter the

channel of interest it must be configured for the job. First the

RESET pin should be pulsed low for a minimum of 30 ns and

should then be returned high. This HARD_RESET of the

AD6620 clears the CIC Accumulators as well as the NCO

Phase Accumulator. When

RESET is brought high the AD6620 is

removed from the HARD_RESET condition. The AD6620 is

now in SOFT_RESET. In this state the Mode Control Register

at address 0x300 contains a “1” (Bit 0 is high). When the AD6620

is in SOFT_RESET, no data is accepted by the input data port

and no processing occurs. The serial port and parallel output

port is held inactive and the chip is defined as a SYNC slave to

avoid possible contentions on these pins. While the AD6620 is

in this condition it should be programmed by the process below.

It should be noted that this initialization must be performed via

the microprocessor port since the serial port is inactive.

1. If the AD6620 is being reinitialized without performing a

HARD_RESET, then address 0x300 should be written 1 to

place the AD6620 in SOFT_RESET. This allows the non-

dynamic registers to be programmed.

2. Program the Coefficient RAM of the AD6620 with the

desired FIR Filter. The address auto-increment feature can

be used to decrease the amount of time required to program

the Coefficients. This feature is described in detail in the

Microport Control section that follows.

3. (Optional) The first piece of data out of the AD6620 is always

zero due to an output pipeline delay. There will also be a

start-up glitch on the output of the AD6620 due to possible

nonzero data in the I and Q data RAMS of the RCF filter.

These RAMS are not initialized by the HARD_RESET. If

this is a concern then the data RAMS should now be written

to zero. For efficiency the auto-increment feature can be

used as with the programming of the coefficient RAMs.

4. The Configuration Registers of the AD6620 are now pro-

grammed. First, address 0x300 should be written to set the

Operating Mode if Diversity Channel Real or Single Channel

Complex Modes are used. Bit 0 of this register should remain

high at this time. This will hold the SOFT_RESET condition.

The remaining configuration registers can now be programmed.

This should start at address 0x301 and continue to address

0x30D. This defines the operation of the NCO and filter stages.

5. The AD6620 is now ready to be removed from SOFT_RESET

and allowed to process data. This is done by writing address

0x300 to again set the desired mode of operation. This loca-

tion should be set for SYNC MASTER or SYNC SLAVE

operation at this time. Bit 0 of this register is written low at

this time to remove the SOFT_RESET condition.

Dynamic Programming of the AD6620

Many attributes of the AD6620 may be altered dynamically as

the AD6620 processes the received data. This allows the receiver

to be adjusted during operation in order to achieve the maxi-

mum performance. The typical dynamic registers of the AD6620

are listed in the following table. To program the other registers

follow the steps described in the section titled Initializing the

AD6620. Technically all registers can be programmed dynami-

cally, but adverse results may occur if registers other those listed

are written dynamically.

These addresses may be programmed via either the Micropro-

cessor or the Serial Control Ports.

Table X. Dynamic AD6620 Registers

Address

Bit Width

Name

302

NCO SYNC CONTROL REGISTER

303

NCO_FREQ

304

NCO PHASE_OFFSET

305

INPUT/CIC2 SCALE REGISTER

307

CIC5 SCALE REGISTER

309

OUTPUT/RCF CONTROL REGISTER

30B

RCF ADDRESS OFFSET REGISTER

Registers 0x302, 0x303 and 0x304 allow the NCO of the AD6620

to be adjusted. The tuning frequency can be dynamically changed

for frequency hopping. The phase of the carrier can be adjusted

with address 0x304. The phase accuracy of the synchronization

can be changed with 0x302. Registers 0x305, 0x307, and 0x309

allow the user to dynamically control the gain of the AD6620 in

6 dB increments. This can be used to maximize the AD6620s

dynamic range for the signal being tuned at a particular instant.

spectral estimation.

In addition to dynamically writing to these registers, they may

also be read to verify program content. Care should be taken,

however, because reading some registers may affect normal chip

operation. In particular, reading from 303h the NCO frequency

will cause the phase accumulator to be reset via the SYNC_NCO

pulse if the AD6620 is running as a Sync master. If the device is

run as a Sync slave, then the phase accumulator is not reset.

Addresses 000h through 1FFh should not be read dynamically

as doing so will disrupt the internal state machine computing

the FIR taps. These locations may be read statically if needed.

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