AD6620SSLASHPCB datasheet(9/44 Pages) AD

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AD6620

–9–

REV. A

MICROPORT MODE0, READ

Timing is synchronous to CLK; MODE = 0.

tDD

DATA VALID

tHC

tSC

tHC

tZD

tHA

tRDY

ADDRESS VALID

tSAM

tZR

N+1

N+2

N+3

N+4

CLK1

WR2

RD2

CS3

D[7:0]

RDY1

A[2:0]

NOTES:

1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE

OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.

2 THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.

3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.

Figure 17. MODE0 Read Timing Requirements and Switching Characteristics

MICROPORT MODE0, WRITE

Timing is synchronous to CLK; MODE = 0.

DATA VALID

tHC

tSC

tHC

tSC

tHM

ADDRESS VALID

N+1

N+2

N+3

CLK1

WR2

RD2

CS3

D[7:0]

RDY

A[2:0]

NOTES:

1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE

RISING EDGE OF CLK "N+2".

2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.

3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.

* THE NEXT WRITE MAY BE INITIATED ON CLK, N*.

tHA

tRDY

tSAM

Figure 18. MODE0 Write Timing Requirements and Switching Characteristics

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