AD6620SSLASHPCB datasheet(19/44 Pages) AD

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AD6620

–19–

REV. A

SCLK

AD6620

DSP

+3.3V

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

Figure 30. Typical Serial Data Output Interface to DSP

(Serial Master Mode, SBM = 1)

Figure 31 shows two AD6620s illustrating the cascade capability

for the chip. The first is connected as a serial master and the

second is configured in serial cascade mode. The SDFE signal

of the master is connected to the SDFS of the slave. This allows

the master AD6620 data to be obtained first by the DSP, fol-

lowed by the cascaded AD6620 data.

SCLK

AD6620

DSP

+3.3V

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

10k

SCLK

AD6620

CASCADE

SBM

SDI

SDO

SDFS

SDFE

SDIV

Figure 31. Typical Serial Data Output Interface to DSP

(Serial Cascade Mode, SBM = 0)

The AD6620 also supports a serial slave mode, where the serial

clock and interface is provided by a DSP or ASIC that is set to

operate in the master mode. Note that the AD6620 cannot be

booted through the serial port. The microport must be used to

initialize the device, then serial operation is supported.

In the serial slave mode, DVOUT is valid and indicates the pres-

ence of a new word in the output buffers of the shift register.

This pin may thus be used by the DSP to generate an interrupt

to service the serial port. The DSP then generates an SFDS

pulse to drive the AD6620. The first serial clock rising edge

after SDFS makes the first bit available at SDO. The falling

edge of serial clock can be used to sample the data. The total

number of bits are then read from the AD6620 (determined by

the serial port word length). If the DSP has the ability to count

bits, the DSP will know when the complete frame is read. If not,

the DSP can monitor the SDFE pin to determine that the com-

plete frame is read. The serial clock provided by the DSP can be

asynchronous with the AD6620 clock and input data.

SCLK

AD6620

DSP

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

DVOUT

IRQ

Figure 32. Typical Serial Data Output Interface to DSP

(Serial Slave Mode, SBM = 0)

In either the serial master or slave mode, there are two con-

straints that must be observed. The first is that the clock must

be fast enough to read the serial frame prior to the next frame

becoming available. Since the AD6620 output is synchronous

with its input sample rate, the output update rate can be deter-

mined by the user-programmed decimation rate. The timing

diagram in Figure 33 details how serial slave mode is imple-

mented. The second constraint is that the time between serial

frames may be either zero SCLK periods (the end of one frame

adjoins the beginning of the next) or two or more SCLK peri-

ods. One SCLK period between frames is not allowed.

tDSO

DVOUT

SCLK

SDFS

SDO

DSP USES FALLING EDGE OF

DVOUT TO GENERATE SDFS

FIRST DATA IS AVAILABLE THE FIRST

RISING SCLK AFTER SDFS GOES HIGH

IMSB

IMSB – 1

DVOUT PULSEWIDTH IS 2 CLKIN

SINGLE CHANNEL AND 4 CLKIN

DUAL CHANNEL

Figure 33. Timing for Serial Slave Mode (SBM = 0)

FREQUENCY TRANSLATOR

The first signal processing stage is a frequency translator con-

sisting of two multipliers and a 32-bit complex numerically

controlled oscillator (NCO). The NCO serves as a quadrature

local oscillator capable of producing any analytic frequency

between –fSAMP/2 and +fSAMP/2 with a resolution of fSAMP/2

32. In

the Single Channel Real input mode, fSAMP is equal to fCLK multi-

plied by the fraction of CLK cycles that A/B is high. In the

Diversity Channel Real and Single Channel Complex input

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