AD6620SSLASHPCB datasheet(40/44 Pages) AD

40 / 44 page

AD6620

–40–

REV. A

bit set mode1 SRD1H | SRD2L | SRRFH | SRRFL;

nop;

* Insert code here to process I and Q data. The DSP serial port handler

has placed the samples in fm_demod_data and fm_demod_data+1

pop sts;

* Pop the status stack */

rti (db);

* Switch back to primary set of DAGs and Register file */

bit clr mode1 SRD1H | SRD2L | SRRFH | SRRFL;

nop;

.ENDSEG;

*—————————————————————————————*/

Software for Diversity Channel Real Operation

The code for interfacing to Diversity Channel Real mode is very

similar to that of single channel. The only difference being the

number of channels allocated on the TDM chain. This process

can easily be extended for any number of TDM channels as

long as there is sufficient time in the frame to completely trans-

mit the data. This procedure works with the appended data as

well as serially cascaded devices. The code below demonstrates

setup and operation in diversity channel mode.

/*—————————————————————————————*/

.SEGMENT/DM dm_data;

* multi-channel register setup */

.VAR fm_demod_data[4];

* Array for receiving 2 real and imag

sample from each channel

.VAR fm_demod_tcb[8] = 0, 0, 0, 0, 0, 4, 1, fm_demod_data;

* Transfer Control Block for reception of fm data */

* —————————————————————————————*/

*—————————————————————————————*/

setup_sport1:

r0 = 0;

* multi-channel enable setup */

dm(MTCS1) = r0;

* do not transmit on any channels */

r0 = 0;

* Compand Setup */

dm(MTCCS1) = r0;

* no companding on transmit */

dm(MRCCS1) = r0;

* no companding on receive */

r0 = 0x00100000;

* Setup sport 1 transmit control register */

dm(STCTL1) = r0;

* mfd = 1 */

r0 = 0x038c00f2;

* Setup sport 1 receive control register */

dm(SRCTL1) = r0;

* slen = 15, sden & schen enabled */

* sign extend, external SCLK+RFS */

r0 = fm_demod_tcb + 7; /

* TCB address */

dm(fm_demod_tcb + 4) = r0;

* TCB point back to itself */

dm(CP1) = r0;

* Kickoff DMA chain */

rts (db)

* RETURN */

bit set imask SPR1I;

* enable sport1 receive interrupt */

bit set imask CB15I;

* Enable circular buffer 15 wrap

interrupt for buffers full

*—————————————————————————————*/

spr1_svc:

jump spr1_asserted;

RTI;

*—————————————————————————————*/

spr1_asserted: /

* SPORT1 Receive interrupt - do the fm demod and

increment the counter

push sts;

* Push the status stack */

* Use secondary set of DAGs and Register file */

SRRFL;

nop;

* Insert code here for processing I and Q data pairs. The DSP serial

port handler has placed the samples in fm_demod_data through

fm_demod_data+3

pop sts;

* Pop the status stack */

rti (db);

* Switch back to primary set of DAGs and Register file */

SRRFL;

nop;

.ENDSEG;

*—————————————————————————————*/

TYPICAL LATENCY EXPECTATIONS

In the AD6620 latency can be divided into three components.

For difficult filters, the largest component of latency is Algorith-

mic Latency. This type of latency is tied inseparably to the desired

filter response. For smaller or minimal filters, Fixed Latency begins

to dominate. This is the undesirable fixed delay associated with

the calculation of the output samples. Finally, Variable Latency,

is the smallest component. This is the delay that can be influenced

by the relative phase of internal decimated clocks with respect to

the SYNC_CIC.

Algorithmic Latency is a necessary component of any filtering

process be it analog or digital. Since frequency is a variation

with respect to time, it must take time to discriminate between

analog frequencies. Assuming the AD6620 is used to generate

linear phase, low-pass filters, the algorithmic latency is a direct

function of the number of RCF taps and the CIC decimation

ratios. In general, the largest part of the impulse response of

these filters is the center of the impulse response length, so that

the delay is represented by one-half the composite impulse

response length.

The impulse response length of the RCF is the number of taps

times the RCF input sample period. Therefore relative to the

input sample clock the impulse response length of the RCF is

given by;

TAPS

CIC

ADC

−

(

) ××

The impulse response length of the CIC5 is given by;

×−

(

) ×+

CIC

ADC

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