AD6620SSLASHPCB datasheet(39/44 Pages) AD

39 / 44 page

AD6620

–39–

REV. A

the SDO of the master AD6620 takes control of the SDO line

and begins shifting data out of the device. When all data has

been shifted, the master raises the SDFE on the last shifted.

This signals the next chip (slave) that on the next cycle of the

clock it should take control of the SDO line and begin shifting

data to the DSP. When the second AD6620 completes its shift,

it raises its SDFE to signal the next chip in the chain, if present.

If additional devices are connected to the chain, this would be

used to indicate they should take control on the next clock cycle.

This application does not have a third device and therefore, the

frame would end.

Normally in an application with a single AD6620, the AD6620

would be configured as the serial bus master. However, there

are applications where the DSP or other device may be the serial

bus master. In this case, the diagram below illustrates how to

configure the AD6620 so that it may be used in this mode. In

order to use this in a meaningful application, the DSP must

know when the AD6620 has new data available on its output. If

the DSP polls the AD6620 too early, either old data will be present

or the data could be in an indeterminate state. To prevent this,

the AD6620 has an output pin DVOUT that signals the DSP

when new data is available. This should be tied to an interrupt

line of the DSP that is edge-sensitive, as the DVOUT line is only

valid for two or four high speed clock cycles depending on the

mode of the chip. The DSP may then invoke an interrupt service

routine to handle the data, see text below. In this application,

the DSP is responsible for generating the framing and clocking

signals to the AD6620 as shown in Figure 51.

SCLK

AD6620

DSP

+3.3V

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

10k

SCLK

SBM

SDI

SDO

SDFS

SDFE

SDIV

AD6620

CASCADE

Figure 50. Dual AD6620s Using the Serial Bus in a TDM

Application

SCLK

AD6620

DSP

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

10k

SBM

DVOUT

IRQ

Figure 51. AD6620 Configured as a Serial Slave

Software for Single Channel Real Operation

When interfacing Analog Device’s SHARC DSP, the following

code fragments can be used to configure the SHARC. The first

example shows how to configure the registers for use with a single

channel application. The first segment of code defines the memory

for use with the multichannel serial port data. The second segment

of code sets up the serial port for receiving data only. It could

have just as easily been set up for bidirectional data by properly

setting the MTCSI register. The final two code segments are used

when a serial port interrupt occurs. When the SHARC detects

completion of the serial port frame, an interrupt is generated

and the final code segment is executed. The comments in that

section show where user code should be inserted. The SHARC

takes care of moving the serial port buffers data directly to data

memory as shown.

* —————————————————————————————*/

* multi-channel register setup */

.SEGMENT/DM dm_data;

.VAR fm_demod_data[2];

* Array for receiving 1 real and imag

sample

.VAR fm_demod_tcb[8] = 0, 0, 0, 0, fm_demod_data+7, 2, 1,

fm_demod_data;

* Transfer Control Block for reception of fm data */

* —————————————————————————————*/

* Subroutine to setup sport1 for use with the AD6620 */

setup_sport1:

r0 = 0;

* multi-channel enable setup */

dm(MTCS1) = r0;

* do not transmit on any channels */

r0 = 0;

* Compand Setup */

dm(MTCCS1) = r0;

* no companding on transmit */

dm(MRCCS1) = r0;

* no companding on receive */

r0 = 0x00100000;

* Setup sport 1 transmit control register */

dm(STCTL1) = r0;

* mfd = 1 */

r0 = 0x038c20f2;

* Setup sport 1 receive control register */

dm(SRCTL1) = r0;

* slen = 15, sden & schen enabled */

* sign extend, external SCLK+RFS */

r0 = fm_demod_tcb + 7; /

* TCB address */

dm(CP1) = r0;

* Kickoff DMA chain */

rts (db);

* RETURN */

bit set imask SPR1I;

* enable sport1 receive interrupt */

nop;

* —————————————————————————————*/

spr1_svc:

jump spr1_asserted;

RTI;

* —————————————————————————————*/

* Process received data here. Data samples located in fm_demod_data

and fm_demod_data+1

spr1_asserted:

push sts;

* Push the status stack */

* Use secondary set of DAGs and Register file */

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