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AD6620S/PCB 数据表(PDF) 23 Page - Analog Devices

部件名 AD6620S/PCB
功能描述  67 MSPS Digital Receive Signal Processor
PDF  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6620S/PCB 数据表(HTML) 23 Page - Analog Devices

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AD6620
–23–
REV. A
The frequency response of the filter is given by the following
equations. The gain and pass band droop of CIC5 should be
calculated by these equations. Both parameters may be compen-
sated for in the RCF stage.
Hz
z
z
S
M
CIC
CIC
()


+
1
2
1
1
5
5
51
5
Hf
Mf
f
f
f
S
CIC
SAMP
SAMP
CIC
()
sin
sin
×




+
1
2
5 5
5
2
2
5
π
π
The scale factor, SCIC5 is a programmable unsigned integer
between 0 and 20. It serves to control the attenuation of the
data into the CIC5 stage in 6 dB increments. For the best dynamic
range, SCIC5 should be set to the smallest value possible (lowest
attenuation) without creating an overflow condition. This can
be safely accomplished using the equation below, where OLCIC2
is the largest fraction of full scale possible at the input to this
filter stage. This value is output from the CIC2 stage then pipe-
lined into the CIC5. SCIC5 is ignored when this filter is bypassed
by setting MCIC5 = 1.
S
ceil
M
OL
OL
M
OL
CIC
CIC
CIC
CIC
CIC
S
CIC
CIC
52
5
5
2
5
5
5
5
2
5
2
5
()
= () ×
+
log (
) –
when CIC5 is bypassed;
OL
OL
CIC
CIC
52
=
The output rate of this stage is given by the equation below.
f
f
M
SAMP
SAMP
CIC
5
2
5
–0.5
–120
–100
–80
–60
–40
–20
0
f/fSAMP
–0.4 –0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
–0.5
–120
–100
–80
–60
–40
–20
0
f/fSAMP2
–0.4 –0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
Figure 37. CIC2 Alias Rejection, MCIC2 = 16
5TH ORDER CASCADED INTEGRATOR COMB FILTER
The third signal processing stage, CIC5, implements a sharper
fixed-coefficient, decimating filter than CIC2. The input rate to
this filter is fSAMP2. The maximum input rate is given by the
equation below. NCH equals two for Diversity Channel Real
input mode; otherwise NCH equals one. In order to satisfy this
equation, MCIC2 can be increased, NCH can be reduced, or fCLK
can be increased (reference fractional rate input timing described
in the Input Timing section).
f
f
N
SAMP
CLK
CH
2
2
×
The decimation ratio, MCIC5, may be programmed from 1 to 32
(all integer values). When MCIC5 = 1, this stage is bypassed and
the CIC5 scale factor is ignored.



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