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AX2000 数据表(PDF) 30 Page - Microsemi Corporation

部件名 AX2000
功能描述  Axcelerator Family FPGAs
PDF  262 Pages
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制造商  MICROSEMI [Microsemi Corporation]
网页  http://www.microsemi.com
标志 MICROSEMI - Microsemi Corporation

AX2000 数据表(HTML) 30 Page - Microsemi Corporation

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Detailed Specifications
2- 16
R e v i sio n 1 8
I/O Clusters
Each I/O cluster incorporates two I/O modules, four RX modules, two TX modules, and a buffer module.
In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one
Enable Register (EnReg) (Figure 2-5).
Using an I/O Register
To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os.
Usage of each I/O register (register combining) is individually controlled and can be selected/deselected
using the PinEditor tool in the Designer software. I/O register combining can also be controlled at the
device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any given
design.4
In addition, Designer software provides a global option to enable/disable the usage of registers in the
I/Os. This option is design-specific. The setting for each individual I/O overrides this global option.
Furthermore, the global set fuse option in the Designer software, when checked, causes all I/O registers
to output logic High at device power-up.
Figure 2-5 •
I/O Cluster Interface
EnReg
DIN
YOUT
Y
DCIN
OutReg
DIN
YOUT
InReg
I/O Cluster
OEP
UOP
UIP
Programmable Delay
Slew Rate
I/O
OEN
UON
UIN
Drive Strength
P PAD
N PAD
Routed Input Track
Routed Input Track
Output Track
Routed Input Track
Routed Input Track
Output Track
Routed Input Track
Routed Input Track
Output Track
EnReg
DIN
YOUT
Y
DCIN
OutReg
DIN YOUT
InReg
Routed Input Track
Routed Input Track
Output Track
Programmable Delay
Slew Rate
I/O
Drive Strength
VREF
VREF
4.
Please note that register combining for multi fanout nets is not supported.



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