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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 73 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 73 Page - Microsemi Corporation |
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73 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 59 Timing Models and Waveforms Timing Characteristics Figure 2-32 • R-Cell Delays E D Q CLR PRESET CLK tSUE tHE tSUD tHD tRCO tWASYN tHASYN tCLR tREASYN tCPWHL tCPWLH tPRESET tWASYN tHASYN tREASYN Table 2-63 • R-Cell Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. R-Cell Propagation Delays tRCO Sequential Clock-to-Q 0.67 0.77 0.90 ns tCLR Asynchronous Clear-to-Q 0.67 0.77 0.90 ns tPRESET Asynchronous Preset-to-Q 0.36 0.36 0.36 ns tSUD Flip-Flop Data Input Set-Up 0.34 0.34 0.34 ns tSUE Flip-Flop Enable Input Set-Up 0.00 0.00 0.00 ns tHD Flip-Flop Data Input Hold 0.67 0.77 0.90 ns tHE Flip-Flop Enable Input Hold 0.67 0.77 0.90 ns tWASYN Asynchronous Pulse Width 0.48 0.48 0.48 ns tREASYN Asynchronous Recovery Time 0.23 0.27 0.31 ns tHASYN Asynchronous Removal Time 0.36 0.36 0.36 ns tCPWHL Clock Pulse Width High to Low 0.36 0.36 0.36 ns tCPWLH Clock Pulse Width Low to High 0.36 0.36 0.36 ns |
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