AX2000 datasheet(82/262 Pages) MICROSEMI

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Detailed Specifications

2- 68

R e v i sio n 1 8

Routed Clocks

The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in

the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0

(Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of

any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals

or high fanout nets. All four CLKs are available everywhere on the chip.

Timing Characteristics

Table 2-75 • AX125 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Units

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Routed Array Clock Networks

tRCKL

Input Low to High

3.08

3.50

4.12

tRCKH

Input High to Low

3.13

3.56

4.19

tRPWH

Minimum Pulse Width High

0.57

0.64

0.75

tRPWL

Minimum Pulse Width Low

0.52

0.59

0.69

tRCKSW

Maximum Skew

0.35

0.39

0.46

tRP

Minimum Period

1.15

1.31

1.54

tRMAX

Maximum Frequency

870

763

649

MHz

Table 2-76 • AX250 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Units

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Routed Array Clock Networks

tRCKL

Input Low to High

2.52

2.87

3.37

tRCKH

Input High to Low

2.59

2.95

3.47

tRPWH

Minimum Pulse Width High

0.57

0.64

0.75

tRPWL

Minimum Pulse Width Low

0.52

0.59

0.69

tRCKSW

Maximum Skew

0.35

0.39

0.46

tRP

Minimum Period

1.15

1.31

1.54

tRMAX

Maximum Frequency

870

763

649

MHz

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