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Axcelerator Family FPGAs

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Table 2-80 • PLL Interface Signals

Signal Name

Type

User

Accessible

Allowable

Values

Function

RefCLK

Input

Yes

Reference Clock for the PLL

Input

Yes

Feedback port for the PLL

PowerDown

Input

Yes

PLL power down control

PLL powered down

PLL active

DIVI[5:0]

Input

Yes

1 to 64, in

unsigned binary

notation offset by

-1

Sets value for feedback divider (multiplier)

DIVJ[5:0]

Input

Yes

Sets value for CLK1 divider

LowFreq

Input

Yes

Input frequency range selector

50–200 MHz

14–50 MHz

Osc[2:0]

Input

Yes

Output frequency range selector

XX0

400–1000 MHZ

001

200–400 MHZ

011

100–200 MHZ

101

50–100 MHZ

111

20–50 MHZ

DelayLine[4:0]

Input

Yes

–15 to +15

(increments), in

signed-and-

magnitude binary

representation

Clock Delay (positive/negative) in increments

of 250 ps, with maximum value of ± 3.75 ns

FBMuxSel

Input

Selects the source for the feedback input

REFSEL

Input

Selects the source for the reference clock

OUTSEL

Input

Selects the source for the routed net output

PLLSEL

Input

ROOTSEL & PLLSEL are used to select the

source of the global clock network

ROOTSEL

Input

Lock

Output

Yes

High value indicates PLL has locked

CLK1

Output

Yes

PLL clock output

CLK2

Output

Yes

PLL clock output

Note:

If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are

indeterminate.

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