AX2000 datasheet(1/262 Pages) MICROSEMI

部件名	AX2000

功能描述	Axcelerator Family FPGAs

PDF	262 Pages

Scroll/Zoom	100%

制造商	MICROSEMI [Microsemi Corporation]

网页	http://www.microsemi.com

标志

1 / 262 page

March 2012

i

Axcelerator Family FPGAs

Leading-Edge Performance

• 350+ MHz System Performance

• 500+ MHz Internal Performance

• High-Performance Embedded FIFOs

• 700 Mb/s LVDS Capable I/Os

Specifications

• Up to 2 Million Equivalent System Gates

• Up to 684 I/Os

• Up to 10,752 Dedicated Flip-Flops

• Up to 295 kbits Embedded SRAM/FIFO

• Manufactured on Advanced 0.15

μm CMOS Antifuse Process

Technology, 7 Layers of Metal

Features

• Single-Chip, Nonvolatile Solution

• Up to 100% Resource Utilization with 100% Pin Locking

• 1.5 V Core Voltage for Low Power

• Footprint Compatible Packaging

• Flexible, Multi-Standard I/Os:

– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

– Bank-Selectable I/Os – 8 Banks per Chip

– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI,

and 3.3 V PCI-X

– Differential I/O Standards: LVPECL and LVDS

– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,

SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

– Registered I/Os

– Hot-Swap Compliant I/Os (except PCI)

– Programmable Slew Rate and Drive Strength on Outputs

– Programmable Delay and Weak Pull-Up/Pull-Down Circuits

on Inputs

• Embedded Memory:

– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18,

x36 Organizations Available)

– Independent, Width-Configurable Read and Write Ports

– Programmable Embedded FIFO Control Logic

• Segmentable Clock Resources

• Embedded Phase-Locked Loop:

– 14-200 MHz Input Range

– Frequency Synthesis Capabilities up to 1 GHz

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Debug Capability with

Microsemi Silicon Explorer II

• Boundary-Scan Testing Compliant with IEEE Standard 1149.1

(JTAG)

• FuseLock™ Programming Technology Protects Against

Reverse Engineering and Design Theft

Table 1 • Axcelerator Family Product Profile

Device

AX125

AX250

AX500

AX1000

AX2000

Capacity (in Equivalent System Gates)

125,000

250,000

500,000

1,000,000

2,000,000

Typical Gates

82,000

154,000

286,000

612,000

1,060,000

Modules

Register (R-cells)

672

1,408

2,688

6,048

10,752

Combinatorial (C-cells)

1,344

2,816

5,376

12,096

21,504

Maximum Flip-Flops

1,344

2,816

5,376

12,096

21,504

Embedded RAM/FIFO

Number of Core RAM Blocks

4

12

16

36

64

Total Bits of Core RAM

18,432

55,296

73,728

165,888

294,912

Clocks (Segmentable)

Hardwired

4

Routed

4

PLLs

88

8

I/Os

I/O Banks

8

Maximum User I/Os

168

248

336

516

684

Maximum LVDS Channels

84

124

168

258

342

Total I/O Registers

504

744

1,008

1,548

2,052

Package

PQ

BG

FG

CQ

CG

256, 324

208

256, 484

208, 352

208

484, 676

208, 352

729

484, 676, 896

352

624

896, 1152

256, 352

624

Revision 18

类似零件编号 - AX2000

制造商	部件名	数据表	功能描述
Microsemi Corporation	AX2000	13Mb / 262P	Axcelerator Family FPGAs
Actel Corporation	AX2000-1BG896	2Mb / 226P	Axcelerator Family FPGAs
	AX2000-1BG896B	2Mb / 226P	Axcelerator Family FPGAs
	AX2000-1BG896I	2Mb / 226P	Axcelerator Family FPGAs
	AX2000-1BG896M	2Mb / 226P	Axcelerator Family FPGAs

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类似说明 - AX2000

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Microsemi Corporation	AX250-PQ208I	13Mb / 262P	Axcelerator Family FPGAs
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