AM79C30AVC datasheet(19/101 Pages) AMD

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Am79C30A/32A Data Sheet

LIU Mode Register (LMR1), Read/Write

Address = Indirect A3H

LMR1 is defined in Table 12.

Notes:

The F and FA bits in LMR1 (bits 2 and 3) should be enabled during the activation procedure so the Am79C30A/32A can respond

with INFO 3.

LMR1 bit 4 is used to transfer the signals PH-AR and Expiry of Timer from the microprocessor to the LIU (see CCITT I.430 state

diagram—activation request). PH-AR is defined as bit 4 being a logical 1 and Expiry of Timer is defined as the transition of bit 4

from a logical 1 to a logical 0. This bit must not be set until the LIU, as reflected in the LSR, is in state F3, F6, or F7 and the

receiver has been enabled for a minimum of 250 µs.

LMR1 bit 6 is primarily used to disable the receiver when the terminal does not require access to the S Interface signals. This bit

is cleared by reset and must be written to logical 1 in order to receive activation from the S Interface, or to request activation.

LIU Mode Register 2 (LMR2), Read/Write

Address = Indirect A4H

LMR2 is used to select the operations found in Table 13.

Table 12.

LIU Mode Register 1

Bit

Logical 1

Logical 0 (default value)

Enable B1 transmit

Disable B1 transmit

Enable B2 transmit

Disable B2 transmit

Disable F transmit

Enable F transmit

Disable FA transmit

Enable FA transmit

Activation request

No activation request

Go from F8 to F3

No transition

Enable receiver/transmitter

Disable receiver/transmitter

Reserved; must be set to logical 0

Table 13.

LIU Mode Register 2

Bit

Logical 1

Logical 0 (Default Value)

D-channel loopback at Am79C30A/32A enable

D-channel loopback at Am79C30A/32A disable

D-channel loopback at LIU enable

D-channel loopback at LIU disable

D-channel back-off disable

D-channel back-off enable

F3 change of state interrupt enable

F3 change of state interrupt disable

F8 change of state interrupt enable

F8 change of state interrupt disable

HSW interrupt enable

HSW interrupt disable

F7 change of state interrupt enable

F7 change of state interrupt disable

Reserved; must be set to logical 0

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