AM79C30AVC datasheet(39/101 Pages) AMD

39 / 101 page

Am79C30A/32A Data Sheet

disabled, the Am79C30A/32A receives the first two

bytes, issues an End of Address interrupt, and receives

the packet. Both a Valid Address and an End of Ad-

dress interrupt set Interrupt Register bit 2 to a logical 1

and bit 0 of the D-channel Status Register 1 (DSR1) to

a logical 1. The Valid Address/End of Address interrupt

can be disabled via DMR3 bit 0. There is an internal

3-byte delay which holds the first of the D-channel ad-

dress bytes until the interrupt has been issued. Note

that the incoming address bytes cannot be read how-

ever, until the D-channel Receive Byte Available or

D-channel Receive Threshold interrupt is set.

After the address is received, the DLC continues to re-

ceive D-channel bytes into the D-channel Receive

buffer FIFO. The DLC issues an interrupt when data is

available in the D-channel Receive buffer. This interrupt

can be disabled by setting DMR3 bit 3 to a logical 0.

The DLC also issues an interrupt when the receive

threshold set in DMR4 is reached. This interrupt can be

disabled by programming a logical 0 into DMR1 bit 1.

By polling, the microprocessor can then read the

D-channel bytes. The 3-byte delay incurred during ad-

dress recognition is maintained. Therefore, the DLC re-

ceives the Frame Check Sequence (FCS) before

issuing an interrupt to signal the last byte of the packet

has been received and appropriate status bits have

been updated. If DMR3 bit 7 is set, the two FCS bytes

at the end of the packet are transferred into the D-chan-

nel Receive buffer along with the data.

The DLC issues an interrupt when the last byte of the

packet is read from the DCRB. This interrupt can be

disabled by setting DMR3 bit 2 to a logical 0.

After the FCS is received, the DLC receiver detects the

closing flag (a bit sequence of 01111110) and then ter-

minates the packet by issuing an End Of Receive

Packet interrupt (bit 1 of DSR1) and returns to looking

for opening flags. The DLC also terminates the packet

when an abort, an overflow, or overrun error condition

is detected. The End Of Receive Packet interrupt can

be disabled by setting DMR1 bit 3 to a logical 0.

The D-channel Receive Byte Count Register (DRCR)

is a 16-bit wide, two-word deep FIFO that is used to

record the number of bytes in the incoming D-channel

packets. Each count is terminated by an end-of-packet

condition. Thus, the DRCR informs the microprocessor

of the number of bytes, including the address bytes,

which have been received. The counter is updated

when the last byte of a packet is placed in the D-chan-

nel Receive buffer. When the FCS bytes are included in

the data transferred to the D-channel Receive buffer,

the FCS bytes are included in the byte count; if the FCS

bytes are not included in the transfer, they are not in-

cluded in the byte count. The opening flag and closing

flag are not included in the byte count.

The D-channel Error and Address Status Registers are

also double buffered. Reading the last byte of a packet

causes the DER byte to propagate to the output of the

FIFO and updates the D-channel Status and Interrupt

Registers accordingly. Reading the MSB of the DRCR

causes the next count and associated ASR byte to

propagate to the output of the FIFOs and updates the

D-channel Status and Interrupt Registers accordingly.

For this reason it is important to read ASR, DER, and

DSR1 prior to reading the DRCR.

When a receive error occurs, an End-of-Packet inter-

rupt is generated and the packet is terminated. When

the last byte of the associated packet is read from the

D-channel Receive buffer, the appropriate DER bits are

set and an error interrupt is generated. All error inter-

rupts can be individually masked by setting the corre-

sponding bits in DMR2 to a logical 0.

There is one 16-bit D-channel Receive Byte Limit Reg-

ister (DRLR). The received byte count is compared with

the DRLR. When the byte count of the currently re-

ceived D-channel packet exceeds the limit value, a re-

ceiver overflow is detected, the packet is terminated,

and an End-of-Packet interrupt is issued. D-channel

Error Register (DER) bit 4 is set to a logical 1 and an

overflow interrupt issued when the last byte of the as-

sociated packet is read from the D-channel Receive

buffer. The Overflow Error interrupt can be masked by

setting DMR2 bit 4 to a logical 0.

The minimum packet length is 5 bytes for a 2-byte ad-

dress packet (not including flags). If the packet length

is less than the above, an interrupt is issued and DER

bit 5 is set to a logical 1 when the last byte of the asso-

ciated packet is read from the D-channel Receive

buffer. The error interrupt can be masked by setting

DMR2 bit 5 to a logical 0.

If packet reception is in progress and the D-channel

Receive buffer is full, the microprocessor has a maxi-

mum of 425

µs to respond to the D-channel Receive

Data Available interrupt. If the microprocessor fails to

do so, then an overrun error occurs when the data byte

is overwritten. When this happens, the packet is termi-

nated. DER bit 6 is set to a logical 1 when the last byte

of the associated packet is read from the D-channel

Receive buffer. The Overrun Error interrupt can be

masked by setting DMR2 bit 6 to logical 0.

Error indication is given if two packets have been re-

ceived and not serviced by the user and a third packet

is received via DSR2 bit 2. When this error occurs, the

third packet is terminated (not received).

Error indication is given for a receiver abort (the recep-

tion of seven contiguous 1s) by DER bit 0.

If the number of bits received between two flags is not

an integer multiple of eight (if the received packet does

not contain an integral number of bytes), DER bit 1 is

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