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AM79C30AVC 数据表(PDF) 23 Page - Advanced Micro Devices |
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AM79C30AVC 数据表(HTML) 23 Page - Advanced Micro Devices |
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23 / 101 page  Am79C30A/32A Data Sheet 23 MUX Control Register 4 (MCR4), Read/Write Address = Indirect 44H The MUX Control Register 4 (MCR4) can prevent interrupt generation by masking the output of IR bit 4. MCR4 has the format shown in Table 19. Table 19. MUX Control Register 4 Bit Logical 1 Logical 0 (Default Value) 0–2 Reserved, must be set to logical 0 Reserved, must be set to logical 0 3 Enable Bb- or Bc-channel byte available interrupt (IR Bit 4) Disable interrupt 4 Reverse bit order of Bb (LSB transmitted/received first) No Bb bit reversal (MSB transmitted/received first) 5 Reverse bit order of Bc (LSB transmitted/received first) No Bc bit reversal (MSB transmitted/received first) 6 Reserved, must be set to logical 0 Reserved, must be set to logical 0 7 Reserved, must be set to logical 0 Reserved, must be set to logical 0 |
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