AM79C30AVC datasheet(17/101 Pages) AMD

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Am79C30A/32A Data Sheet

Transmission of Q bits

The microprocessor can load the Multiframe Q-bit

buffer (MFQB) once the Q-bit buffer empty bit (bit 6 of

the Multiframe S bit/Status buffer) is set. The Q-bit

buffer empty bit is set to a logical 1 at reset or when

data that has been written to the Multiframe Q-bit buffer

is transferred to the LIU. The Q-bit buffer empty bit is

cleared to a logical 0 when the Multiframe S-bit/Status

buffer is read. After multiframing has been requested

and established, the Am79C30A/32A transfers the data

written into the Q-bit Register to the LIU, synchronized

to the multiframe, irrespective of the receipt of valid

Q-control bits. If the microprocessor does not reload

the Q-bit Register for retransmissions, the Q-bit pattern

is repeated in the next multiframe.

If multiframing is enabled but multiframe synchroniza-

tion is not established, the LIU transmits the value

loaded in MFQB bit 4 in all Q bits. The default value of

MFQB bit 4 is a logical 0 which satisfies the CCITT rec-

ommendations. When synchronization is achieved, the

contents of MFQB bits 3 to 0 are transmitted according

to Table 8.

Loss of Multiframe Synchronization

The Am79C30A/32A continuously monitors the FA

(Q-bit control) and the M bits to ensure multiframe syn-

chronization. Once multiframe synchronization is es-

tablished, multiframe synchronization is lost if three

consecutive invalid multiframes are received, or the LIU

is no longer in state F6 or F7, or multiframing is dis-

abled. When loss of multiframe synchronization occurs,

bit 7 of the Multiframe Register is set to a logical 0, and

bit 7 of the Multiframe S bit/Status buffer is set to a

logical 1. The Am79C30A/32A also terminates the re-

ception of S bits and transmission of Q bits until multi-

framing synchronization is re-established.

HSW

The hookswitch circuitry on the DSC circuit provides the

attached microprocessor with a way of converting an

external mechanical hookswitch into a software status

condition capable of generating an interrupt. Debounce

and glitch rejection are provided internal to the DSC cir-

cuit. The logic rejects glitches less than 162 ns and pro-

vides debounce of 16 ms. HSW status reporting is

disabled after RESET. It is enabled by any of the follow-

ing: taking the device out of Idle mode, a write to a MUX

Control Register (MCR3–MCR1), or unmasking the

HSW interrupt.

Table 8.

Multiframing Structures

Frame Number

NT-to-TE Q Control Bit FA

NT-to-TE M Bit (M)

NT-to-TE S Bit (S)

TE-to-NT FA Bit (Q Bit)

SC11

SC21

SC31

SC41

SC51

SC12

SC22

SC32

SC42

SC52

SC13

SC23

SC33

SC43

SC53

SC14

SC24

SC34

SC44

SC54

SC11

SC21

etc.

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