AM79C30AVC datasheet(21/101 Pages) AMD

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Am79C30A/32A Data Sheet

Multiframe S-bit/Status Buffer (MFSB), Read Only

Address = Indirect A7H

The MFSB reset default value is 40H.

Multiframe Q-bit Buffer (MFQB), Write Only

Address = Indirect A8H

Multiplexer (MUX)

The MUX contains the registers found in Table 17.

The Multiplexer is used to selectively route 64-Kbit/s

full-duplex B channels between the LIU (Line Interface

Unit), MAP (Main Audio Processor), MPI (Microproces-

sor Interface), and the PP (Peripheral Port).

The logical channels available at the MUX are shown in

Figure 2, They are:

1. From/to the LIU channels B1 and B2

2. From/to the MAP channel Ba

3. From/to the MPI channels Bb and Bc

4. From/to the PP channels Bd, Be, and Bf

For any specific application, the MUX can be pro-

grammed by the microprocessor to route any three

B- ch annel por ts to any othe r three B- channel

ports.Programmable bidirectional bit reversal is pro-

vided for both of the MPI data channels Bb and Bc.

MUX Control Registers 1, 2, and 3

(MCR1, MCR2, and MCR3), Read/Write

Addresses = Indirect 41H, 42H, 43H

The MUX can support three bidirectional paths. The

contents of the MUX Control Registers MCR1, MCR2,

and MCR3 direct the flow of data between the eight

MUX logical B channels (see Figure 2). These three

MCRs are programmed to connect any two B-channel

ports together by writing the appropriate channel code

into an MCR. These MCRs have the same format,

where bits 7–4 indicate port 1 and bits 3–0 indicate port

2. In each of these three MCR registers, the channel

codes found in Table 18 are used for both ports 1 and 2.

For example, to connect B1(LIU) with Bb (MPI) and B2 (LIU)

with Ba (MAP), the contents of the MCRs would be:

Table 15.

Multiframe S-Bit/Status Buffer

Bit

Description

Generates Interrupt

0S1

S-data available

If MF bit 1 = 1

Q-bit buffer empty

If MF bit 2 = 1

Multiframe change of state

If MF bit 3 = 1

Table 16.

Multiframe Q-Bit Buffer

Bit

Description

Q1 (default = 1)

Q2 (default = 1)

Q3 (default = 1)

Q4 (default = 1)

Q-bit value when multiframing enabled but

synchronization not achieved (default = 0)

5, 6, 7

Not used

Table 17.

MUX Registers

No./Registers

Mnemonic

MUX Control

Registers

MCR1, MCR2, MCR3,

MCR4

Table 18.

MCR Register Channel Codes

Code

Channel

0000

No connection (default value)

0001

B1 (LIU)

0010

B2 (LIU)

0011

Ba (MAP)

0100

Bb (MPI)

0101

Bc (MPI)

0110

Bd (PP channel 1)

0111

Be (PP channel 2)

1000

Bf (PP channel 3)

Port 1

Port 2

MCR1

0 0 0 1 0 1 0 0 B1 (LIU)

Bb (MPI)

MCR2

0 0 1 0 0 0 1 1 B2 (LIU)

Ba (MAP)

MCR3

0 0 0 0 0 0 0 0 No connect

No connect

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