STM32F207IE datasheet(83/163 Pages) STMICROELECTRONICS

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STM32F205xx, STM32F207xx

Electrical characteristics

Doc ID 15818 Rev 7

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5.3.11

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 37: EMI characteristics). It is available only on the main PLL.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

An amplitude quantization error may be generated because the linear modulation profile is

obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage

quantized modulation depth is given by the following formula:

Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is fPLL_OUT nominal.

Tmode is the modulation period.

md is the modulation depth.

Table 31.

SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max(1)

Unit

fMod

Modulation frequency

KHz

Peak modulation depth

0.5

dec

MODEPER * INCSTEP

215

−1dec

Guaranteed by design, not tested in production.

MODEPER

round f

PLL_IN

Mod

()

⁄

[]

INCSTEP

round

–

() md f

VCO_OUT

() 100 5

MODEPER

()

⁄

[]

quantized%

MODEPER

INCSTEP

100

()

–

() f

VCO_OUT

()

⁄

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