STM32F207IE datasheet(22/163 Pages) STMICROELECTRONICS

22 / 163 page

Description

STM32F205xx, STM32F207xx

22/163

Doc ID 15818 Rev 7

Otherwise, PA0 should be asserted low externally during POR until VDD reaches

1.8 V (see Figure 7).

In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the

1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in

OFF.

●

Regulator OFF/internal reset OFF

On WLCSP66 package, this mode activated by connecting REGOFF to VSS and

IRROFF to VDD. IRROFF cannot be activated in conjunction with REGOFF. This mode

is available only on the WLCSP package. It allows to supply externally a 1.2 V voltage

source through VCAP_1 and VCAP_2 pins, in addition to VDD.

The following conditions must be respected:

–VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection

between power domains (see Figure 6).

–

PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach

1.08 V, and until VDD reaches 1.65 V.

–

NRST should be controlled by an external reset controller to keep the device

under reset when VDD is below 1.65 V (see Figure 7).

Figure 6.

Startup in regulator OFF: slow VDD slope

- power-down reset risen after VCAP_1/VCAP_2 stabilization

This figure is valid both whatever the internal reset mode (ON or OFF).

STM32F207IE 数据表(PDF) 22 Page - STMicroelectronics