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STM32F207IE 数据表(PDF) 91 Page - STMicroelectronics |
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STM32F207IE 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 163 page  STM32F205xx, STM32F207xx Electrical characteristics Doc ID 15818 Rev 7 91/163 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source ±20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). ● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). Output voltage levels Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 42. Output voltage characteristics(1) 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Symbol Parameter Conditions Min Max Unit VOL (2) 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V -0.4 V VOH (3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V -0.4 V VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 - VOL (2)(4) 4. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 2.7 V < VDD < 3.6 V -1.3 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–1.3 - VOL (2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 2 V < VDD < 2.7 V -0.4 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - |
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