STM32F207IE datasheet(20/163 Pages) STMICROELECTRONICS

20 / 163 page

Description

STM32F205xx, STM32F207xx

20/163

Doc ID 15818 Rev 7

2.2.14

Boot modes

At startup, boot pins are used to select one out of three boot options:

●

Boot from user Flash

●

Boot from system memory

●

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB

OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

2.2.15

Power supply schemes

●

VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins. On WLCSP package, VDD ranges from

1.65 to 3.6 V.

●

VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

●

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Refer to Figure 17: Power supply scheme for more details.

Note:

VDD/VDDA minimum value of 1.65 V is obtained when the device operates in a reduced

temperature range.

2.2.16

Power supply supervisor

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and

ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the

option byte loading process starts, either to confirm or modify default thresholds, or to

disable BOR permanently. Three BOR thresholds are available through option bytes.

The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or

VBOR, without the need for an external reset circuit. On devices in WLCSP package, BOR

can be inactivated by setting IRROFF to VDD (see Section 2.2.17: Voltage regulator).

The device also features an embedded programmable voltage detector (PVD) that monitors

the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be

generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

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