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STM32F207IE 数据表(PDF) 127 Page - STMicroelectronics |
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STM32F207IE 数据表(HTML) 127 Page - STMicroelectronics |
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127 / 163 page  STM32F205xx, STM32F207xx Electrical characteristics Doc ID 15818 Rev 7 127/163 Figure 61. Synchronous non-multiplexed PSRAM write timings Table 74. Synchronous non-multiplexed PSRAM write timings(1)(2) 1. CL = 15 pF. 2. Preliminary values. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 16.6 ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) THCLK + 2 ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) TCK + 2 ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high THCLK + 1 ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low 6 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns |
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