STM32F415VG datasheet(104/186 Pages) STMICROELECTRONICS

104 / 186 page

Electrical characteristics

STM32F415xx, STM32F417xx

104/186

DocID022063 Rev 4

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) =

±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

An amplitude quantization error may be generated because the linear modulation profile is

obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage

quantized modulation depth is given by the following formula:

As a result:

Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is fPLL_OUT nominal.

Tmode is the modulation period.

md is the modulation depth.

Figure 35. PLL output clock waveforms in center spread mode

INCSTEP

round

–

() md PLLN

() 100 5

MODEPER

()

⁄

[]

INCSTEP

round

–

() 2 240

() 100 5

250

()

⁄

[]

126md(quantitazed)%

mdquantized%

MODEPER INCSTEP

100

()

–

() PLLN

()

⁄

mdquantized%250 126

100

()

–

() 240

()

⁄

2.002%(peak)

Frequency (PLL_OUT)

Time

tmode

ai17291

2 x tmode

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