5CSXFC6D datasheet(2/35 Pages) ALTERA

2 / 35 page

Supporting Feature

Advantage

• Requires only two core voltages to operate

• Available in low-cost wirebond packaging

• Includes innovative features such as Configuration via Protocol

(CvP) and partial reconfiguration

Lowest system cost

Summary of Cyclone V Features

Table 2: Summary of Features for Cyclone V Devices

Description

Feature

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Technology

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless

migration between different device densities

• RoHS-compliant and leaded

(1)options

Packaging

Enhanced 8-input ALM with four registers

High-performance FPGA fabric

• M10K—10-kilobits (Kb) memory blocks with soft error correction code

(ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where

you can use up to 25% of the ALMs as MLAB memory

Internal memory blocks

• Native support for up to three signal processing

precision levels (three 9 x 9, two 18 x 18, or one 27 x 27

multiplier) in the same variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Variable-precision

DSP

Embedded Hard IP blocks

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC

support

Memory controller

PCI Express

® (PCIe®) Gen2 and Gen1 (x1, x2, or x4) hard

IP with multifunction support, endpoint, and root port

Embedded

transceiver I/O

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic

power

Clock networks

(1) Contact Altera for availability.

Cyclone V Device Overview

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Summary of Cyclone V Features

2013.12.26

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