5CSXFC6D datasheet(3/35 Pages) ALTERA

3 / 35 page

Description

Feature

• Precision clock synthesis, clock delay compensation, and zero delay buffering

(ZDB)

• Integer mode and fractional mode

Phase-locked loops (PLLs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS

transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

FPGA General-purpose I/Os

(GPIOs)

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

Low-power high-speed serial

interface

• Single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz

maximum frequency with support for symmetric and asymmetric

multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC),

USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface

(QSPI) flash controller, NAND flash controller, Secure

Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I

2C interface, and up to 85

HPS GPIO interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory

access (DMA) controller, FPGA configuration manager, and clock and reset

managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and

lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue

transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable

interface to the multiport front end (MPFE) of the HPS SDRAM controller

• ARM CoreSight

™ JTAG debug access port, trace port, and on-chip trace

storage

HPS

(Cyclone V SE, SX, and ST

devices only)

• Tamper protection—comprehensive design protection to protect your

valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Partial and dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel

(FPP) x8 and x16 configuration options

Configuration

Altera Corporation

Cyclone V Device Overview

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Summary of Cyclone V Features

CV-51001

2013.12.26

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