Total RAM Bit (Kb)

MLAB

M10K

Member

Code

Variant

RAM Bit (Kb)

Block

RAM Bit (Kb)

Block

4,884

424

679

4,460

446

D5

Cyclone V GT

7,696

836

1338

6,860

686

D7

13,917

1,717

2748

12,200

1,220

D9

1,538

138

221

1,400

140

A2

Cyclone V SE

2,460

231

370

2,700

270

A4

4,450

480

768

3,970

397

A5

5,761

621

994

5,570

557

A6

1,538

138

221

1,400

140

C2

Cyclone V SX

2,460

231

370

2,700

270

C4

4,450

480

768

3,970

397

C5

5,761

621

994

5,570

557

C6

4,450

480

768

3,970

397

D5

Cyclone V ST

5,761

621

994

5,570

557

D6

Embedded Memory Configurations

Table 19: Supported Embedded Memory Block Configurations for Cyclone V Devices

This table lists the maximum configurations supported for the embedded memory blocks. The information is

applicable only to the single-port RAM and ROM modes.

Programmable Width

Depth (bits)

Memory Block

x16, x18, or x20

32

MLAB

x40 or x32

256

M10K

x20 or x16

512

x10 or x8

1K

x5 or x4

2K

x2

4K

x1

8K

Clock Networks and PLL Clock Sources

Cyclone V devices have 16 global clock networks capable of up to 550 MHz operation. The clock network

architecture is based on Altera's global, quadrant, and peripheral clock structure. This clock structure is

supported by dedicated clock input pins and fractional PLLs.

To reduce power consumption, the Quartus II software identifies all unused sections of the clock

network and powers them down.

Note:

Altera Corporation

Cyclone V Device Overview

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21

Embedded Memory Configurations

CV-51001

2013.12.26