Power Management

Leveraging the FPGA architectural features, process technology advancements, and transceivers that are

designed for power efficiency, the Cyclone V devices consume less power than previous generation Cyclone

FPGAs:

• Total device core power consumption—less by up to 40%.

• Transceiver channel power consumption—less by up to 50%.

Additionally, Cyclone V devices contain several hard IP blocks that reduce logic resources and deliver

substantial power savings of up to 25% less power than equivalent soft implementations.

Document Revision History

Changes

Version

Date

• Corrected single or dual-core ARM Cortex-A9 MPCore processor-up

to 925 MHz from 800 MHz.

• Removed "Preliminary" texts from Ordering Code figures, Maximum

Resources, Package Plan and I/O Vertical Migration tables.

• Removed the note "The number of GPIOs does not include transceiver

I/Os. In the Quartus II software, the number of user I/Os includes

transceiver I/Os." for GPIOs in the Maximum Resource Counts table

for Cyclone V E and SE.

• Added link to Altera Product Selector for each device variant.

2014.12.26

December 2013

• Updated Embedded Hard IPs for Cyclone V GT devices to indicate

Maximum 2 hard PCIe and 2 hard memory controllers.

• Added leaded package options.

• Removed the note "The number of PLLs includes general-purpose

fractional PLLs and transceiver fractional PLLs." for all PLLs in the

Maximum Resource Counts table.

• Corrected max LVDS counts for transmitter and receiver for Cyclone V

E A5 device from 84 to 60.

• Corrected max LVDS counts for transmitter and receiver for Cyclone V

E A9 device from 140 to 120.

• Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18

multiplier adder mode and 18 x 18 multiplier adder summed with 36

bit input for Cyclone V SE devices from 58 to 84.

• Corrected 18 x 18 multiplier for Cyclone V SE devices from 116 to 168.

• Corrected 9 x 9 multiplier for Cyclone V SE devices from 174 to 252.

• Corrected LVDS transmitter for Cyclone V SE A2 and A4 as well as SX

C2 and C4 devices from 31 to 32.

• Corrected LVDS receiver for Cyclone V SE A2 and A4 as well as SX C2

and C4 devices from 35 to 37.

• Corrected transceiver speed grade for Cyclone V ST devices ordering

code from 4 to 5.

Cyclone V Device Overview

Altera Corporation

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Power Management

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2013.12.26