CS4360

DS517PP1

9

-40 to +85°C; VLS = 1.7 V to 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VLS CL = 20 pF)

Notes: 15. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

Parameters

Symbol

Min

Typ

Max

Units

Input Sample Rate

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

4

50

100

-

-

-

50

100

200

kHz

kHz

kHz

LRCK Duty Cycle

45

50

55

%

MCLK Duty Cycle

405060

%

SCLK Frequency

-

-MCLK/2

Hz

SCLK Frequency

Note 15

-

-MCLK/4

Hz

SCLK rising to LRCK edge delay

20

-

-

ns

SCLK rising to LRCK edge setup time

20

-

-

ns

SDATA valid to SCLK rising setup time

20

-

-

ns

SCLK rising to SDATA hold time

20

-

-

ns

Figure 1. Serial Mode Input Timing

sclkh

t

slrs

t

slrd

t

sdlrs

t

sdh

t

sclkl

t

SDATA

SCLK

LRCK