CS4360 datasheet(24/36 Pages) CIRRUS

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CS4360

DS517PP1

the power or exiting the power-down state. If not, a

transient will occur when the audio outputs are ini-

tially clamped to GND. The time that the device

must remain in the power-down state is related to

the value of the DC-blocking capacitance. For ex-

ample, with a 3.3 µF capacitor, the minimum pow-

er-down time will be approximately 0.4 seconds.

Use of the Mute Control function is recommended

for designs requiring the absolute minimum in ex-

traneous clicks and pops. Also, use of the Mute

Control function can enable the system designer to

achieve idle channel noise/signal-to-noise ratios

which are only limited by the external mute circuit.

See the CDB4360 data sheet for a suggested mute

circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set-

tings. The operation of the control port may be

completely asynchronous with the audio sample

rate. However, to avoid potential interference prob-

lems, the control port pins should remain static if

no operation is required.

The CS4360 has MAP auto increment capability,

enabled by the INCR bit in the MAP register,

which is the MSB. If INCR is 0, then the MAP will

stay constant for successive writes. If INCR is set

to 1, then MAP will auto increment after each byte

is written, allowing block reads or writes of succes-

sive registers.

7.1

Enabling the Control Port

On the CS4360 the control port pins are shared

with stand-alone configuration pins. To enable the

control port, the user must set the CPEN bit. This

is done by performing a Two-Wire or SPI write.

Once the control port is enabled, these pins are ded-

icated to control port functionality.

To prevent audible artifacts the CPEN bit (see Sec-

tion 4.5.2) should be set prior to the completion of

the Stand-Alone power-up sequence, approximate-

ly 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048

LRCK cycles in Quad-Speed Mode). Writing this

bit will halt the Stand-Alone power-up sequence

and initialize the control port to its default settings.

Note, the CPEN bit can be set any time after RST

goes high; however, setting this bit after the Stand-

Alone power-up sequence has completed can cause

audible artifacts.

7.2

Format Selection

The control port has 2 formats: SPI and Two-Wire,

with the CS4360 operating as a slave device.

If Two-Wire operation is desired, AD0/CS should

be tied to VLS or GND. If the CS4360 ever detects

a high to low transition on AD0/CS after power-up

and after the control port is activated, SPI format

will be selected.

7.3

Two-Wire Format

In Two-Wire Format, SDA is a bidirectional data

line. Data is clocked into and out of the part by the

clock, SCL, with a clock to data relationship as

shown in Figure 5. The receiving device should

send an acknowledge (ACK) after each byte re-

ceived. There is no CS pin. Pin AD0 form the par-

tial chip address and should be tied to VLS or GND

as required. The upper 6 bits of the 7 bit address

field must be 001000.

Note, MCLK is required during all two-wire trans-

actions. The Two-Wire format is compatible with

the I2C protocol. Please see reference 2 for further

details.

7.3.1

Writing in Two-Wire Format

To communicate with the CS4360, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (low for a write). The next byte is the

Memory Address Pointer, MAP, which selects the

lowed by the data to be written. To write multiple

registers, continue providing a clock and data,

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